The invention includes a design structure embodied in a computer readable medium for performing a method for inserting a
scan chain into a VLSI
circuit design. The
scan chain structure, or structures, are included in the design structure for the VLSI
circuit design. The
scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in
normal mode operation, in scan mode operation, in initialization mode and in
low leakage power mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain. Buffer circuit control elements control the first flip-flop (L1) to switch between scan mode or low power leakage mode. The switching occurs in only one
clock cycle. The design structure can include a
netlist, which describes the VLSI circuit, reside on storage medium as a
data format used for the exchange of
layout data of integrated circuits, and preferably includes at least one of
test data files, characterization data,
verification data, or design specifications.