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305results about How to "Increase the footprint" patented technology

Wafer level package including a device wafer integrated with a passive component

According to an exemplary embodiment, a wafer level package includes a device wafer including at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The wafer level package includes a first polymer layer situated over the device wafer. The wafer level package includes at least one passive component situated over the first polymer layer and having a first terminal and a second terminal. The first terminal of the at least one passive component is electrically connected to the at least one device wafer contact pad. The wafer level package includes a second polymer layer situated over the at least one passive component. The wafer level package includes at least one polymer layer contact pad situated over the second polymer layer and electrically connected to the second terminal of the at least one passive component.
Owner:SKYWORKS SOLUTIONS INC

Thermally enhanced low parasitic power semiconductor package

A method and structure for a dual heat dissipating semiconductor device. A method includes attaching a drain region on a first side of a die, such as a power metal oxide semiconductor field effect transistor (MOSFET) to a first leadframe subassembly. A source region and a gate region on a second side of the die are attached to a second leadframe subassembly. The first leadframe subassembly is attached to a third leadframe subassembly, then the device is encapsulated or otherwise packaged. An exposed portion of the first leadframe subassembly provides an external heat sink for the drain region, and the second leadframe subassembly provides external heat sinks for the source region and the gate region, as well as output leads for the gate region. The third leadframe subassembly provides output leads for the drain region.
Owner:TEXAS INSTR INC
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