173results about How to "Improved yield" patented technology

The present invention is characterized in having a process for forming a pattern by making a substrate having an insulating property, such as a liquid-repellent thin film over a substrate, such as a semiconductor film, selectively have affinity for liquid by plasma generating means 102, and discharging a drop compound to the surface having affinity for liquid by a drop discharging means 103. By putting the region having affinity for liquid, which was selectively formed, between liquid-repellent, a drop after drop landing can be formed without moving the drop landing portion

An on-the-go monitor and control means and method for an agriculture machines includes on-the-go soil sensors that can be used to control tillage and seeding depth. On seeder implements, the sensors provide information that affects uniform plant emergence.

A display device, comprising: a) a display having a plurality of pixels including one or more defective pixel(s) and one or more additional pixel(s); and b) a controller for driving the display pixels and for transforming an input signal into a compensated signal for selectively modifying the output of one or more additional pixel(s) in the display to compensate for the output of the defective pixel(s).

An improved semiconductor wafer processing apparatus 10 includes a series of processing stations combined in one form, coupled together by computer-controlled cluster tooling. Wafers are supplied in a pod to an input station 28 which initiates a data record for recording processing results at each station. A sacrificial film 140 is applied to the surface 135 of each wafer. Individual wafers are transferred to a computer-controlled defect-mapping station 14 where particulate defects 130 are identified and their position coordinates recorded. Defect-mapped wafers are transferred to a computer-controlled laser area cleaning station 11 which lifts the defects and sweeps the wafer surface clean, except for stubborn defects. Clean wafers are transferred to a final mapping station 20 or 22, followed by transfer of the wafers to an output station 30. Wafers having remaining stubborn defects are transferred to a second defect-mapping station 16 where stubborn defects are located by coordinates, after which the wafers are transferred to a defect review tool incorporating a scanning electron microscope (SEM-DRT) 24. A SEM image review of stubborn defects includes chemical analysis of the stubborn defects. A laser point-cleaning station 13 lifts and sweeps each stubborn defect individually from the wafer surface. Cleaned wafers are transferred to a third defect-mapping station 18 for recording any stubborn defects remaining, then to a second laser area cleaning station 12 for a final cleaning, followed by transfer of the wafers to a final mapping station 20 or 22 for mapping of any remaining stubborn defects. The accompanying data records are updated followed by transfer of the wafers to an output station 30.

A solar cell includes: an photoelectric conversion body including a first main surface and a second main surface opposed to the first main surface; a first electrode provided on the first main surface; a second electrode provided on the second main surface; a first conductive connection member connected with the first electrode for connecting the solar cell and another solar cell, wherein the first conductive connection member includes a conductive soft layer at an area facing the first electrode, and the first electrode includes a conductive soft layer at an area facing the first conductive connection member; and a first resin adhesive bonding the first conductive connection member to the first electrode in such a manner that the conductive soft layer of the first electrode and the conductive soft layer of the first conductive connection member abut on each other.

A display device having a plurality of driving elements and wiring parts electrically connected to the driving parts, the display device includes: a plurality of first electrodes which are formed in correspondence to each driving element on the driving elements and the wiring parts; a plurality of light-emitting parts which are each formed on the first electrodes; a common second electrode which is formed from a material that transmits light from the light-emitting part and is formed on the light-emitting parts; auxiliary wiring parts with a lower resistance than the second electrodes; and contact parts which are formed in laminate structure from a plurality of conductive layers and which electrically connect the second electrodes and the auxiliary wirings with each other, with at least the lowermost conductive layer of the conductive layers of the contact parts being in direct contact with the second electrode.

A method for automatically wiring (i.e., routing) an integrated circuit chip after completing the placement of cells on the chip is described. The method employs a maze routing such that the spacing between the routed wires is increased, while at the same time maintaining control over the total wiring length. The maze routing herein described is modified to improve chip yield, reduce wiring capacitance, limit power consumption and coupled signal noise, all of which are achieved by increasing wire-to-wire spacings.

The present invention relates to novel Tenofovir disoproxil hemifumarate salt, which is prepared by dealkylation of Phosphonate esters by using mineral acids followed by esterification and crystallization to give crystalline Tenofovir disoproxil. The Tenofovir disoproxil is further converted to fumarate salts with improved yield.

Disclosed is a technique capable of improving a yield of a semiconductor device by measuring a plurality of TEGs arranged in a scribe region. A first electrode pad connected to each terminal of a TEG is formed as a rectangular, minute, isolated pattern having a side length of about 0.5 μm or shorter and constituted of an uppermost layer wiring on a semiconductor substrate, and therefore, a great number of TEGs can be laid in a first scribe region. The characteristic evaluation or the failure analysis is performed by contacting a nanoprobe having a tip radius of curvature of 0.05 μm to 0.8 μm to the first electrode pad.

A water-solible polymer dispersion, p process for producing the same and a method of use therefor. In particular, the water-soluble polymer dispersion is one comprising water-soluble polymer fine particles of 100 μm or less diameter having at least one ionic property selected from among cationic, amphoteric, nonionic and anionic properties together with a polyalkyleneimine and / or a product of polyalkyleneimine modification wherein according to necessity an appropriate amount of water-soluble inorganic salt is incorporated. The provided process enables easily performing the production in dispersed form by means of production facilities of low cost. The obtained water-soluble polymer dispersion is excellent in storage stability and exhibits satisfactory fluidity and solubility so as to enable use in papermaking raw material pretreatments added to papermaking raw materials prior to machine operation and also for enhancement of freeness, increase of sizing degree and enhancement yield. Further use can be found in incorporation in an organic sludge or paper mill sludge for flocculation and ensuing drainage.

A method of and system for evaluating performance of a plant population in an area of interest is provided. The method includes the steps of receiving input data from a user, the input data representative of at least one management parameter in the group consisting of: a total plant population in a selected sampling sub-area, a spacing of an individual plant relative to a nearest adjacent plant in the sampling sub-area, and a maturity of the individual plant relative to the nearest adjacent plant in the sampling sub-area. The system analyzes the input data in accordance with a mathematical model having an objective function for predicting a performance of a plant stand represented by a net effective plant population reduced from a benchmark plant population by deduction factors related to at least one of the management parameters.

The present invention provides a MEMS and a sensor having the MEMS which can be formed without a process of etching a sacrifice layer. The MEMS and the sensor having the MEMS are formed by forming an interspace using a spacer layer. In the MEMS in which an interspace is formed using a spacer layer, a process for forming a sacrifice layer and an etching process of the sacrifice layer are not required. As a result, there is no restriction on the etching time, and thus the yield can be improved.

A surface-mount capacitor includes a multilayer capacitor structure formed by laminating plate-like capacitor elements each having anode lead portions 11 at opposite ends thereof and a cathode portion 12 at the center, an anode terminal 18 connected to each anode lead portion 11 via a strip-like plate 14, and a cathode terminal 19 connected to the cathode portion 12. The anode and the cathode terminals 18 and 19 have a flat shape and are formed on a common plane as a substrate-mounted surface. A mold resin case 20 has a bottom portion filling a gap between the anode and the cathode terminals 18 and 19 and mechanically connecting the anode and the cathode terminals 18 and 19, and side walls substantially perpendicular to the substrate-mounted surface. The anode and the cathode terminals 18 and 19 have upper surfaces exposed on an inner bottom surface of the mold resin case 20 to be connected to the anode lead portions 11 and the cathode portion 12.

A semiconductor integrated circuit includes a wiring capable of connecting a plurality of chips on a wafer and has a configuration which is capable of cutting the wiring electrically and which allows all the chips to be tested at one time. Specifically, an exclusive test circuit region capable of being shared for testing the plurality of chips is formed on the wafer, and a test circuit is removed from each chip. Terminals of the chips and a terminal of the test circuit are connected through a wiring on the wafer or a device outside the wafer to enable a general test to be performed in burn-in.

A light emitting device can include a head portion including a surface including a convex portion, a back surface on the opposite side, and a through hole penetrating a tip surface of the convex portion and the back surface; a light-transmitting member including a surface and a back surface on the opposite side, the back surface including a first recess to be fitted to the convex portion; an adhesive bonding part of the surface of the head portion around the convex portion to the back surface of the light-transmitting member while the convex portion is fitted to the first recess and the first recess covers the through hole; a semiconductor light emitting element that emits light passing through the through hole for irradiation of the light-transmitting member; and an optical system condensing the light from the semiconductor light emitting element and locally irradiates the light-transmitting member with the light.

Provided is a method of manufacturing a ceramic multi-layer circuit substrate. A plurality of ceramic blocks, in each of which one or more ceramic green sheets having via-electrodes are layered one atop the other, are formed and are then fired. The fired ceramic blocks are aligned with each other. One or more bonding green sheets each having bonding electrodes in positions corresponding to the via-electrodes of the ceramic blocks are prepared. Each of the bonding green sheets is interposed between a pair of the ceramic blocks opposing each other. The ceramic blocks and the bonding green sheets are bonded and are then fired.

The present invention provides a thermosetting type die bond film that can be preferably broken by tensile force. It is a thermosetting type die bond film used for a method of obtaining a semiconductor element from a semiconductor wafer by forming a reforming region by irradiating the semiconductor wafer with a laser beam and then breaking the semiconductor wafer in the reforming region or a method of obtaining a semiconductor element from a semiconductor wafer by forming grooves that do not reach the backside of the semiconductor wafer on a surface thereof and then exposing the grooves from the backside by grinding the backside of the semiconductor wafer, wherein the elongation rate at break at 25° C. before thermal curing is larger than 40% and 500% or less.

The present invention provides a micro light emitting-diode display panel and a manufacturing method thereof. The first electrode contact and the second electrode contact are alternatively disposed on the base substrate of the micro light-emitting-diode display panel, and the first electrode contact and the second electrode contact are respectively connected with the bottom electrode and the connection electrode of the micro light-emitting-diode. The connection electrode is also connected the top electrode of the micro light-emitting-diode, and the micro light-emitting-diodes can be immediately inspected after the micro-light-emitting-diode is transferred, to reduce the difficulty of detection and product repair, and to improve the product yield.

A tension apparatus for extending a patterning slit sheet included in a thin film deposition apparatus that can be simply applied to produce large-sized display devices on a mass scale and that improves manufacturing yield. The tension apparatus, wherein a plurality of patterning slits are formed along a first direction in the patterning slit sheet, and distances between adjacent patterning slits are different from each other, includes: a light source disposed to face the patterning slit sheet and irradiating light toward the patterning slit sheet; a tension member combined to at least one end of the patterning slit sheet, and applying a predetermined tensile force on the patterning slit sheet; and a master glass onto which light irradiated from the light source and passed through the patterning slit sheet is projected.

In a display apparatus, a display panel receives a driving signal from a driving chip through a pad and displays an image in response to the driving signal. The driving chip includes a terminal outputting the driving signal. The driving chip is mounted on the display panel using the anisotropic conductive film and electrically connected to the display panel. A lubricant layer is formed on a surface of the anisotropic conductive film to prevent an electrical defect in the connection between the driving chip and the display panel. Thus, the display apparatus may have improved yield.

An electromagnetic wave absorber is formed by injection-molding a thermoplastic resin blended with approximately 20-60% by volume of soft magnetic material powder, and blended with a molding assistant and a kneading assistant. The electromagnetic wave absorber includes a unit cell having a bore extending from a top face to a bottom face. A portion of the bore located more adjacently to the bottom face than to the top face has a smaller cross-sectional area than the bore at the top face, and a height of the unit cell from the bottom face to the top face is approximately at least 1.2 times and approximately at most 10 times as large as the maximum width of the bore at the top face of the unit cell.

A bus bar unit is configured to supply power to coils (16) of a plurality of phases, and includes phase bus bars (47U ), (47V), and (47W) which are provided for each phase and are connected to winding start ends of the coils, and a neutral point bus bar (81) which is connected to winding finish ends of the coils, the neutral point bus bar (81) being formed by bending an elongated plate-shaped member such that a width direction of the elongated plate-shaped member and a radial direction of the bus bar unit coincide with each other, and including a plurality of bus bar pieces (82) and a connection portion (83) which connects the bus bar pieces (82) and (82) adjacent to each other, and a width of a deformation portion (85) of the connection portion (83) being narrower than a width of the bus bar piece (82).

The embodiments of the present invention provide a flexible display substrate and a manufacturing method thereof, as well as a flexible display device, which relate to the technical field of display, and can avoid the performance of the thin film transistor from being influenced by light energy when a flexible substrate is striped from a carrying substrate. The method for manufacturing the flexible display substrate may comprise: forming a flexible substrate on a carrying substrate; forming a first buffer layer on the flexible substrate; forming a plurality of display elements on the first buffer layer, each of the plurality of display elements comprising a thin film transistor and an electrode structure, the thin film transistor comprising a metal oxide semiconductor active layer; stripping the flexible substrate from the carrying substrate, wherein the method further comprises: forming a light absorbing layer before the plurality of display elements are formed.

A catalyst for synthesis reaction that can allow the cross coupling reaction at an improved yield, and yet can be collected after used for the reaction and recycled, and a synthesizing method for a compound using the same catalyst for synthesis reaction. In the Suzuki cross-couplings given by the following reaction formula (15), palladium containing perovskite-like composite oxide is used as a catalyst for synthesis reaction:

The invention relates to isolated polynucleotides from Corynebacterium glutamicum which are useful in the regulation of gene expression. In particular, the invention relates to isolated polynucleotides comprising C.glutamicum promoters which may be used to regulate, i.e., either increase or decrease, gene expression. In certain embodiments, isolated promoter sequences of the present invention regulate gene expression through the use of exogenous or endogenous induction. The invention further provides recombinant vectors and recombinant cells comprising isolated polynucleotides of the present invention, preferably in operable association with heterologous genes. Also provided are methods of regulating bacterial gene expression comprising growth of a recombinant cell of the present invention. In particular, the present invention provides methods to regulate genes involved in amino acid production comprising growth of a recombinant cell of the present invention. In certain embodiments, the present invention provides methods of regulating gene expression in bacteria, particularly Corynebacterium species, especially of the genus Corynebacterium, comprising fermentation growth of a recombinant cell of the present invention, where metabolite concentrations, temperature, or oxygen levels are manipulated to regulate gene expression.

It is an object of the present invention to manufacture a minute TFT having an LDD region through process with the reduced manufacturing steps, and form a TFT having a structure suitable for each circuit. It is also an object of the present invention to secure an ON current even in a TFT having an LDD region. A hat-shaped gate electrode is formed by forming a two-layer gate electrode in which the gate length of a lower layer of the gate electrode is longer than that of an upper layer of the gate electrode. The hat-shaped gate electrode is formed by etching only the upper layer of the gate electrode by making the use of the resist recess width. In addition, silicide is formed in a contact portion of a wiring and a semiconductor film to lower contact resistance.

It has been difficult to highly accurately measure the profiles of samples using scanning probe microscopes at the time when scanning is performed due to scanning mechanism fluctuations in the non drive direction, i.e., vertical direction. The present invention is provided with, on the rear side of a sample stage, a high-accuracy displacement gauge for measuring fluctuation in the non drive direction, i.e., vertical direction, at the time when the sample stage is being scanned in the horizontal directions, and as a result, highly accurate planarity evaluation with accuracy of sample nm-order or less is made possible by correcting sample surface shape measurement results obtained using a probe.

A method of manufacturing a semiconductor device includes: (A) a wafer process; and (B) a bias application process after the wafer process. The wafer process includes: (a) forming a n-type well in a p-type semiconductor substrate; (b) forming a p-type well in the n-type well; and (c) forming a transistor on the p-type well, the transistor having a n-type source / drain diffusion layer. In the bias application process, a forward bias is applied between the p-type well and the n-type well to move heavy metal ions.

The present invention relates to a wafer cleaning and a wafer bonding method using the same that can improve a yield of cleaning process and bonding property in bonding the cleaned wafer by cleaning the wafer using atmospheric pressure plasma and cleaning solution. The wafer cleaning method includes the steps of providing a process chamber with a wafer whose bonding surface faces upward, cleaning and surface-treating the bonding surface of the wafer by supplying atmospheric pressure plasma and a cleaning solution to the bonding surface of the wafer, and withdrawing out the wafer from the process chamber. The wafer bonding method includes the steps of: providing a first process chamber with a first wafer whose bonding surface faces upward; cleaning and surface-treating the bonding surface of the first wafer by supplying atmospheric pressure plasma and a cleaning solution to the bonding surface of the first wafer; withdrawing out the first wafer from the first process chamber and providing a second process chamber with the first wafer; providing a third process chamber with a second wafer whose bonding surface faces upward; cleaning and surface-treating the bonding surface of the second wafer by supplying atmospheric pressure plasma and a cleaning solution to the bonding surface of the second wafer; withdrawing out the second wafer from the third process chamber and providing the second process chamber with the second wafer whose bonding surface faces to the bonding surface of the first wafeη and bonding the bonding surfaces of the first and second wafers to each other.

There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of semiconductor chips, resin layers which are disposed on surfaces of the semiconductor chips in which the electrode pads are formed and expose the internal connection terminals, and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals, a wiring substrate on which the plurality of semiconductor apparatuses are stepwise stacked, the wiring substrate electrically connected to the plurality of semiconductor apparatuses, and a sealing resin with which the plurality of semiconductor apparatuses are sealed.