31results about How to "Improve ladder coverage" patented technology

The invention provides an LED (Light Emitting Diode) chip provided with a stepped current blocking structure and a fabricating method thereof. The fabricating method comprises the steps of: providing at least one LED epitaxial wafer comprising a substrate and a light emitting epitaxial structure on the LED epitaxial wafer; fabricating the stepped current blocking structure on the surface of the LED epitaxial wafer vertical to a region of a first electrode correspondingly prefabricated; and fabricating transparent conductive layers on the surfaces of the LED epitaxial wafer and the stepped current blocking structure, and then fabricating a first electrode, a second electrode and a protective layer correspondingly. According to the LED chip provided with a stepped current blocking structure and the fabricating method of the LED chip provided with the stepped current blocking structure provided by the invention, the gradient at the edge of the stepped current blocking structure is slowed so that the contact area of the transparent conductive layer and the stepped current blocking structure is increased, the situation that the transparent conductive layer (ITO) on the side wall (at the step) at the edge of the current blocking structure becomes thinner and even breaks can be avoided, the step covering capacity of the transparent conductive layer is improved, the current spreading capacity of the transparent conductive layer is further improved, the electro-optical conversion efficiency of the LED chip is increased, and the brightness of the LED chip is enhanced.

The invention provides a display system with a capacitive touch panel and a manufacturing method thereof. The display system with a capacitive touch panel comprises a substrate, an electrode circuit, a plurality of signal lines, a dielectric layer and an electrode bridging structure, wherein the electrode circuit is provided with a first electrode and a second electrode, the first electrode comprises a plurality of first conductive patterns, the second electrode comprises a plurality of second patterns, and the first conductive patterns are mutually electrically connected; the plurality of signal lines are formed on the substrate; the dielectric layer is formed on the electrode circuit and covers the electrode circuit; and in the invention, the electrode bridging structure with uniform thickness is formed on the dielectric layer by using a metal open repair technique, so that the second patterns are mutually electrically connected.

The invention discloses a method of forming a grid wall layer, including the following steps that: a substrate with at least a grid is provided; the method of atomic layer deposit is utilized to form a complex medium layer in the substrate; a side wall layer is formed in the grid by etching the complex dielectric layer. The invention is not only favorable to improve the performance of the parts with lower heat budgeting, but also improves the uniformity of the performance of the parts with better uniformity of the formed grid side wall layer.

The invention discloses a semiconductor element isolating structure and a forming method thereof. The forming method of the semiconductor element isolating structure comprises the following steps: firstly, providing a substrate with at least one shallow-groove isolating structure; then, carrying out a metal silicification process to form a dent on the surface of the shallow-groove isolating structure; forming a covering layer to cover the substrate and fill the dent; etching the covering layer to remove the covering layer outside the dent; and finally, forming a contact window etching-stopping layer to cover the substrate and fill the dent. The covering layer is filled in the dent in advance so that the contact window etching-stopping layer covered on the substrate and filled in the dent can not generate gaps or holes.

The invention relates to a method for preparing copper leads for a flat display substrate, comprising the steps of: providing a substrate, forming a crystal seed layer on the surface of the substrate, forming a photoresistance layer with pattern on the surface of the crystal seed layer to expose part of the surface of the crystal seed layer and plating a copper lead layer on the partial exposed surface of the crystal seed layer, where the plating electrolyte comprises sulfur-containing compound. In addition, the contact surface between the prepared copper lead layer and the crystal seed layer makes an included angle greater than 0 deg. but less than 90 deg. with the surface of the copper lead layer. Thus, the prepared copper leads can improve the step covering property in the follow-up course and reduce produced holes and form inclined angles without traditional complex etching process.

The invention firstly provides a substrate comprising plural connection pads, successively at least makes a plasma auxiliary chemical vapour deposition process to deposit a dielectric layer on the substrate surface, where the vapour deposition process is made in a high frequency-low frequency plasma alternating mode, and finally makes an anisotropic etching process to form plural openings in the dielectric layer, where these openings correspond to the connection pads and side wall of each opening is inclined outward.

A barrier film having excellent step coverage is formed, and furthermore, increase of wiring resistance is suppressed, at the time of forming the barrier film on an exposed surface of an interlayer insulating film, which is on a substrate and has a recessed section formed thereon, and forming copper wiring electrically connected to metal wiring on a lower layer side in the recessed section. An oxide film on a surface of the copper wiring which is on the lower layer side and exposed from the bottom surface of the recessed section formed on the interlayer insulating film is reduced or etched and oxygen on the surface of the copper wiring is removed. Then, manganese oxide, i.e., a self-formed barrier layer, is selectively grown on an oxygen containing portion, such as the side walls of the recessed section and a surface of the interlayer insulating film by supplying an organic metal compound which contains manganese but no oxygen, while the manganese oxide is prevented from growing on the surface of the copper wiring. Then, the recessed section is filled with copper.

A flash memory unit forming method comprises the steps as follows: a substrate is provided; a liner oxidation layer and an etching stop layer are formed sequentially on the surface of the substrate; at least two active areas are included in the substrate, and the adjacent active areas are isolated by a shallow trench isolation structure; the etching stop layer and the liner oxidation layer on the surface of the substrate are sequentially removed; a tunneling oxidation layer is formed on the surface of the substrate by a chemical vapor deposition method; and the tunneling oxidation layer is subjected to later stage oxidizing annealing treatment. The flash memory unit forming method provided by the invention avoids the double-hump effect and the reverse narrow channel effect, and the flash memory unit is better in period durability.

The invention discloses a method for preparing a conductive polymer cathode in a solid-state aluminum electrolytic capacitor, and belongs to the field of solid-state aluminum electrolytic capacitors. The method comprises the following steps: pre-depositing a conductive layer on the surface of an anode foil dielectric layer by adopting a chemical vapor deposition method; preparing a conductive polymer on the surface of the deposited conductive layer through an electrochemical method to form a composite conductive layer in a solid-state aluminum electrolytic capacitor; and carrying out cathode electrode extraction on the composite conductive layer to obtain the conductive polymer cathode. According to the invention, the adopted chemical vapor deposition technology avoids the problem that solution molecules are difficult to enter tiny holes in the surface of the anode aluminum foil in an impregnation method and a chemical polymerization method, and effectively avoid the damage of the solution to the dielectric layer.

The invention discloses a semiconductor element isolating structure and a forming method thereof. The forming method of the semiconductor element isolating structure comprises the following steps: firstly, providing a substrate with at least one shallow-groove isolating structure; then, carrying out a metal silicification process to form a dent on the surface of the shallow-groove isolating structure; forming a covering layer to cover the substrate and fill the dent; etching the covering layer to remove the covering layer outside the dent; and finally, forming a contact window etching-stopping layer to cover the substrate and fill the dent. The covering layer is filled in the dent in advance so that the contact window etching-stopping layer covered on the substrate and filled in the dent can not generate gaps or holes.

The invention relates to a zirconium oxide film, a deposition method and application thereof. The zirconium oxide film ZrO2 deposition method includes: depositing a zirconium oxide film by a chemicalvapor deposition method, and supplying a cyclopentyl methyl ether solvent before supplying a zirconium source during deposition. According to the invention, a cyclopentyl methyl ether solvent is usedas an additive to promote the flow of a zirconium source, so that the problem of non-uniform film caused by local excessive deposition can be avoided.

The present invention provides a semiconductor device and an open structure of the semiconductor device, in particular to an opening structure in a semiconductor device with improved step coverage. The opening structure comprises a dielectric layer overlying a substrate and having at least one via opening to expose the substrate. Wherein the via opening comprises a step region in the upper portion of the via opening and a concave profile region with respect to the dielectric layer in the lower portion of the via opening. The semiconductor device and the open structure of the semiconductor device of the present invention is capable of improving the percentage of coverage of the metal step and further improving the reliability of the device.

A method for sputtering an aluminum layer on a surface of a semiconductor device is presented. The method includes three sputtering steps for depositing the aluminum layer, where each sputtering stepincludes at least one sputtering parameter that is different from a corresponding sputtering parameter of another sputtering step. The surface of the semiconductor device includes a dielectric layer having a plurality of openings formed through the dielectric layer.

The invention provides a semiconductor assembly and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a first sealing ring and a second sealing ring whichare separated from each other on a substrate; forming a protective layer on the substrate for covering the first sealing ring and the second sealing ring, wherein the portion, between the first sealing ring and the second sealing ring, of the protective layer is provided with a concave surface; removing the protective layer at the concave surface and a part of the protective layer on the first sealing ring, forming a gap wall on the side wall of the first sealing ring, and forming an opening in the protective layer, wherein the width of the opening is greater than that of the first sealing ring, and the opening enables the top surface of the first sealing ring and the clearance wall to be exposed.

The present invention relates to a pattern structure for an electronic component and a manufacturing method of the pattern structure. The pattern structure includes a pattern layer, a blocking structure, a cantilever structure, and a connection structure; the pattern layer is disposed on a substrate; the blocking structure is disposed on the substrate at one side of the pattern layer; the thickness of the blocking structure is smaller than the thickness of the pattern layer; the cantilever structure is connected between the pattern layer and the blocking structure; and the connection structureis connected between the pattern layer and the substrate at one side of the pattern layer, and is located on the cantilever structure and the blocking structure. The pattern structure provided by thetechnical schemes of the invention has better step coverage performance.

The present invention provides a film forming method for controlling holocrystalline hemispheric granule in small size by a combination etching treatment. The film forming method of a film formed on surface of the treated object W comprises a host crystal formed on the surface of the treated object by film forming gas, the host crystal grows, the HSG film forming process one the surface of the HSG film formed by holocrystalline hemispheric granule is formed; a hemispherical grained (HSG) film is oxidized to form an oxidized layer at the surface part of the HSG film, and then the oxidized layer is etched to be removed. Thus, the film forming method controls the holocrystalline hemispheric granule in small size by a combination etching treatment.

The invention discloses a method of forming a grid wall layer, including the following steps that: a substrate with at least a grid is provided; the method of atomic layer deposit is utilized to form a complex medium layer in the substrate; a side wall layer is formed in the grid by etching the complex dielectric layer. The invention is not only favorable to improve the performance of the parts with lower heat budgeting, but also improves the uniformity of the performance of the parts with better uniformity of the formed grid side wall layer.

The invention provides an LED (Light Emitting Diode) chip provided with a stepped current blocking structure and a fabricating method thereof. The fabricating method comprises the steps of: providing at least one LED epitaxial wafer comprising a substrate and a light emitting epitaxial structure on the LED epitaxial wafer; fabricating the stepped current blocking structure on the surface of the LED epitaxial wafer vertical to a region of a first electrode correspondingly prefabricated; and fabricating transparent conductive layers on the surfaces of the LED epitaxial wafer and the stepped current blocking structure, and then fabricating a first electrode, a second electrode and a protective layer correspondingly. According to the LED chip provided with a stepped current blocking structure and the fabricating method of the LED chip provided with the stepped current blocking structure provided by the invention, the gradient at the edge of the stepped current blocking structure is slowed so that the contact area of the transparent conductive layer and the stepped current blocking structure is increased, the situation that the transparent conductive layer (ITO) on the side wall (at the step) at the edge of the current blocking structure becomes thinner and even breaks can be avoided, the step covering capacity of the transparent conductive layer is improved, the current spreading capacity of the transparent conductive layer is further improved, the electro-optical conversion efficiency of the LED chip is increased, and the brightness of the LED chip is enhanced.

The present invention relates to a method for producing a thin film, the method comprising: a step (i) for adsorbing a growth inhibitor for forming a thin film represented by chemical formula 1 onto the surface of a substrate; and ii) adsorbing a Ti-based thin film precursor onto the surface of the substrate to which the growth inhibitor for thin film formation has been adsorbed. According to thepresent invention, by suppressing side reactions, reducing the growth rate of a thin film, and removing process by-products in the thin film, the step coverage rate and the thickness uniformity of thethin film are greatly improved even when the thin film is formed on a substrate having a complex structure. Chemical formula 1: AnBmXo, where A is carbon or silicon, B is hydrogen or an alkyl group having 1 to 3 carbon atoms, X is halogen, n is an integer of 1 to 15, o is an integer of 1 or more, and m is 0 to 2n+1.

The invention firstly provides a substrate comprising plural connection pads, successively at least makes a plasma auxiliary chemical vapour deposition process to deposit a dielectric layer on the substrate surface, where the vapour deposition process is made in a high frequency-low frequency plasma alternating mode, and finally makes an anisotropic etching process to form plural openings in the dielectric layer, where these openings correspond to the connection pads and side wall of each opening is inclined outward.