Flash memory unit forming method

Abstract

A flash memory unit forming method comprises the steps as follows: a substrate is provided; a liner oxidation layer and an etching stop layer are formed sequentially on the surface of the substrate; at least two active areas are included in the substrate, and the adjacent active areas are isolated by a shallow trench isolation structure; the etching stop layer and the liner oxidation layer on the surface of the substrate are sequentially removed; a tunneling oxidation layer is formed on the surface of the substrate by a chemical vapor deposition method; and the tunneling oxidation layer is subjected to later stage oxidizing annealing treatment. The flash memory unit forming method provided by the invention avoids the double-hump effect and the reverse narrow channel effect, and the flash memory unit is better in period durability.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for forming a flash memory unit. Background technique [0002] The standard physical structure of flash memory is called a flash cell (bit). The structure of the flash memory cell is different from that of conventional MOS transistors. The gate (gate) of a conventional MOS transistor and the conductive channel are separated by a gate insulating layer, generally an oxide layer (oxide); while the flash memory is on the control gate (CG: control gate, which is equivalent to the gate of a conventional MOS transistor). There is also a floating gate (FG: floating gate) between the conductive channel. Due to the existence of the floating gate, the flash memory can complete three basic operation modes: reading, writing, and erasing. Even in the absence of power supply, the existence of the floating gate can maintain the integrity of the stored data. Adjacent flash memory cells ...

AI Technical Summary

Problems solved by technology

[0009] However, existing flash memory cells are prone to double peak effect and reverse narrow channel effect

In addition, the cycle durability of existing transistors is relatively poor

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