48results about How to "Improve device reliability" patented technology

In a stacked chip configuration, and manufacturing methods thereof, the gap between a lower and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with such voids. The present invention is applicable to both chip-level bonding and wafer-level bonding approaches. A photosensitive polymer layer is applied to a first chip, or wafer, prior to stacking the chips or stacking the wafers. The photosensitive polymer layer is partially cured, so that the photosensitive polymer layer is made to be structurally stable, while retaining its adhesive properties. The second chip, or wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips/wafers is greatly improved, while providing complete gap fill. In addition, mechanical reliability is improved, alleviating the problems associated with cracking and delamination, and leading to an improvement in device yield and device reliability.

A manufacturing method for a semiconductor device is provided, wherein a silicon germanium (Si_1-xGe_x; SiGe) layer and a strained silicon layer are sequentially formed on a semiconductor substrate. A gate oxide layer and a gate structure are further formed on the strained silicon layer. The gate structure and the strained silicon layer are heavily doped with n-type dopants to form a compressed gate and source/drain regions, respectively. A cap layer is further formed over the semiconductor substrate, followed by conducting an annealing process. The cap layer is subsequently removed.

Provided is a cleaning agent for electronic materials, which enables very efficient advanced cleaning such that yield in the production of the electronic materials is improved and cleaning in a short period of time becomes possible, the cleaning agent having excellent cleaning power for fine-grained particles and organic matter and being able to reduce metallic contamination on the substrate. The cleaning agent for electronic materials comprises sulfamic acid (A), an anionic surfactant having at least one sulfonic acid group or a salt thereof in the molecule (B), a chelating agent (C), and water, wherein the pH at 25 C is preferably not more than 3.0 and the (B) is preferably a polymeric anionic surfactant (B1) having a weight average molecular weight of 1,000 to 2,000,000.

A process for forming a microelectromechanical system (MEMS) device by a deep reactive ion etching (DRIE) process during which a substrate overlying a cavity is etched to form trenches that breach the cavity to delineate suspended structures. A first general feature of the process is to define suspended structures with a DRIE process, such that the dimensions desired for the suspended structures are obtained. A second general feature is the proper location of specialized features, such as stiction bumps, vulnerable to erosion caused by the DRIE process. Yet another general feature is to control the environment surrounding suspended structures delineated by DRIE in order to obtain their desired dimensions. A significant problem identified and solved by the invention is the propensity for the DRIE process to etch certain suspended features at different rates. In addition to etching wider trenches more rapidly than narrower trenches, the DRIE process erodes suspended structures more rapidly at greater distances from anchor sites of the substrate being etched. At the masking level, the greater propensity for backside and lateral erosion of certain structures away from substrate anchor sites is exploited so that, at the completion of the etch process, suspended structures have acquired their respective desired widths.

An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a dielectric layer, a composite plug and a conductive line. The dielectric layer is disposed on the substrate covering the conductive part. The composite plug is disposed in the dielectric layer electrically connecting with the conductive part, and includes a first plug and a second plug on the first plug, wherein the material or the critical dimension of the second plug is different from that of the first plug. The conductive line is disposed on the dielectric layer electrically connecting with the composite plug.

A semiconductor device includes a semiconductor substrate having a plurality of isolation regions, a plurality of trenches, where each of the plurality of trenches is formed in a corresponding isolation region, of the plurality of isolation regions, and where the plurality of trenches are arranged, in parallel, along a first direction, a plurality of gate lines formed on the semiconductor substrate in a second direction crossing the plurality of trenches, an insulating layer formed between each of the plurality of gate lines, a first air gap formed in at least one of the plurality of trenches, the first air gap extending in the first direction, and a second air gap formed in at least one of the insulating layers, the second air gap extending in the second direction.

A nonvolatile semiconductor memory device includes transistor-based memory cells. Each memory cell has a first and a second source/drain region, a channel region separating the first and the second source/drain region, a storage layer and a control gate. The control gates of the memory cells are connected to word lines. The first and second source/drain regions are connected to bit lines respectively. Each memory cell may be programmed by injecting first charge carriers of a first polarity and may be erased by injecting second charge carriers having the opposite polarity into the storage layer respectively. By applying a high stress voltage between bit line and word line, weak insulator structures may break through such that they become detectable as short-circuits by a low voltage leakage test. By applying the stress voltage contemporaneously on both sides of the memory cells, an early overerase/overprogram, resulting from hot carrier injection, is avoided.

An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a dielectric layer, a composite plug and a conductive line. The dielectric layer is disposed on the substrate covering the conductive part. The composite plug is disposed in the dielectric layer electrically connecting with the conductive part, and includes a first plug and a second plug on the first plug, wherein the material or the critical dimension of the second plug is different from that of the first plug. The conductive line is disposed on the dielectric layer electrically connecting with the composite plug.

A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

The invention concerns a device for measuring the pH of an effluent, said device comprising means for measuring an item of information representative of the pH of said effluent intended to be brought into contact with said effluent.

According to the invention, such a device further comprises means for modifying the pH value of said effluent close to said means for measuring.

The present invention relates to a semiconductor device having a P-channel semiconductor region and a manufacturing method therefor. The method comprises: forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer; blanket pre-doping the gate material layer to introduce an N-type dopant thereto; and pre-doping with fluorine a region of the gate material layer designed to be said P-channel semiconductor device, such that the fluorine dopes an interface between the substrate and the region of the gate dielectric layer designated to be said P-channel semiconductor device. The semiconductor device further comprises an N-type semiconductor region in said gate material layer.

A method of forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a substrate region. The method also includes forming a pad oxide layer overlying the substrate region. The method additionally includes forming a stop layer overlying the pad oxide layer. Furthermore, the method includes patterning the stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a height. Also, the method includes depositing alternating layers of oxide and silicon nitride to at least fill the trench, the oxide being deposited by an HDP-CVD process. The method additionally includes performing a planarization process to remove a portion of the silicon nitride and oxide layers. In addition, the method includes removing the pad oxide and stop layers.

This invention generally relates to an optoelectronic device and a method of fabricating such a device, and more particularly to an optoelectronic device comprising an anode layer, a semiconductive layer provided over the anode layer, and a cathode layer provided over the semiconductive layer, the anode layer comprising a plurality of electrically conductive tracks connected together and spaced apart from one another with gaps therebetween, the device further comprising a first and one or more further hole injection layers provided between the anode layer and the semiconductive layer and extending across said gaps, wherein the first hole injection layer has a conductivity greater than the conductivity of the one or more further hole injection layers.

A method for filling a trench includes forming a first layer in a trench in order to partially fill the trench, removing at least a potion of the first layer from the trench; and forming a second layer on the first layer, wherein the forming a second layer is performed at a temperature of at least 700 degrees C. and at a gas flow ratio of at least 1.6, the gas flow ratio being equal to a first gas flow rate for a first gas to a second gas flow rate for a second gas. In a specific embodiment, the method includes removing a contaminant from the first layer by reacting with the contaminant present in the first layer at the temperature and with the gas flow ratio. In a specific embodiment, the removing at least a portion of the first layer includes etching the portion of the first layer.