85results about How to "Reduce interconnection" patented technology

The invention relates to an integrated circuit package, in particular an integrated chip size package or an integrated chip scale package, comprising a substrate carrying a die, and connection elements, interconnection elements, connecting pins of said die with said connection elements, and a mold encapsulating said die on said substrate. To increase reliability and to reduce failure due to deformation stress, the invention provides said mold with reduced stiffness at areas located substantially at one of said interconnection elements providing increased flexibility of said package at said areas compared to other areas of said package.

An integrated circuit interconnect module for reducing interconnections between integrated circuit chips MOUNTED ON a support substrate. At least one primary integrated circuit (IC) device chip and a plurality of interacting peripheral integrated chip devices. The interconnect module including a plurality of interface pins, each integrated circuit device having a plurality of interface ports. At least one interface port of which is connected to another one of said plurality of integrated circuit devices, at least one of said integrated circuit devices having an interface port connected to an interface pin whereby the majority of nodes on the interacting peripheral devices are adapted to interface with nodes of the primary IC devices in such a way as to condense the number of nets so that the total number of nodes connected to external pins is minimized.

The semiconductor device comprises a lower interconnection part 12 which is formed on a silicon substrate 10 and includes an inter-layer insulation film 36 formed of a low-k film 32 and a hydrophilic insulation film 34 formed on the low-k film 32, and an interconnection layer 44a, 44b buried in interconnection trenches 38a, 38b formed in the inter-layer insulation film 36 and having an interconnection pitch which is a first pitch; and an intermediate interconnection part 14 which is formed on the lower interconnection part 12 and includes an inter-layer insulation film 142 formed of low-k films 136, 140, an interconnection layer 152a, 152b buried in interconnection trenches 146a, 146b formed in the inter-layer insulation film 142 and having an interconnection pitch which is a second pitch larger than the first pitch, and an SiC film 154 formed directly on the low-k film 140 and the interconnection layer 152a, 152b.

In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a shift register which performs discharge of a node and pull-down of an output signal and achieves a small area and low power consumption without using an output signal from a subsequent circuit.

In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signals, only one interchip interconnection that serves for signal transmission is selected and other interchip interconnections are electrically isolated by means of switches that are provided between the interchip interconnections and signal lines. Interchip interconnection capacitance relating to the charge and discharge of interconnections is thus minimized.

An array processor includes processing elements (00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33) arranged in clusters (e.g., 44, 46, 48, 50) to form a rectangular array (40). Inter-cluster communication paths (88) are mutually exclusive. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path, thus eliminating half the wiring required for the path. The length of the longest communication path is not directly determined by the overall dimension of the array, as in conventional torus arrays. Rather, the longest communications path is limited by the inter-cluster spacing. Transpose elements of an N×N torus may be combined in clusters and communicate with one another through intra-cluster communications paths. Transpose operation latency is eliminated in this approach. Each PE may have a single transmit port (35) and a single receive port (37). Thus, the individual PEs are decoupled from the array topology.

In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signals, only one interchip interconnection that serves for signal transmission is selected and other interchip interconnections are electrically isolated by means of switches that are provided between the interchip interconnections and signal lines. Interchip interconnection capacitance relating to the charge and discharge of interconnections is thus minimized.

A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input / output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input / output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input / output bits and passing through the memory cell array chips in the direction of stacking.

A compact air pump and valve package includes pump and valve assemblies integral with a pressure housing defining inlet ports and a plurality of fittings for connecting air lines to an interior of the pressure housing. The linear diaphragm pump assembly has a permanent magnetic shuttle mounting two diaphragms reciprocated by an electromagnet. The valve assembly has a plurality of solenoid valves disposed within the pressure housing, each solenoid valve being operable to control flow into or out of the pressure housing through an associated one of the plurality of fittings. Thus, no tubes or hoses are required to transfer air from the pump assembly to the valves. The housing has special mounts to isolate vibration arising from movement of the shuttle.

A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input / Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I / O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I / O pads of the device are arranged such that additional mechanical support for the device is required.

The semiconductor device comprises a lower interconnection part 12 which is formed on a silicon substrate 10 and includes an inter-layer insulation film 36 formed of a low-k film 32 and a hydrophilic insulation film 34 formed on the low-k film 32, and an interconnection layer 44a, 44b buried in interconnection trenches 38a, 38b formed in the inter-layer insulation film 36 and having an interconnection pitch which is a first pitch; and an intermediate interconnection part 14 which is formed on the lower interconnection part 12 and includes an inter-layer insulation film 142 formed of low-k films 136, 140, an interconnection layer 152a, 152b buried in interconnection trenches 146a, 146b formed in the inter-layer insulation film 142 and having an interconnection pitch which is a second pitch larger than the first pitch, and an SiC film 154 formed directly on the low-k film 140 and the interconnection layer 152a, 152b.

The invention relates to a connector (10) for connecting welding torch where the connector comprises a connector body (12) made of electrically insulating material, a cylindrical current transferring body (30) fitted on the cylindrical front part (13) of the connector body (12), made of electrically conductive material, where the current transferring body (30) has a threaded surface (32) and a side contact surface (35) besides the threaded surface (32) on its side surface, a threaded bore (37) on the side contact surface (35) for fixing current cable with screwed joint and a frontal contact surface (33), further an attachment bracket (60), made of electrically insulating plastic, the attachment bracket (60) has a sleeve part (62), which encircles space apart the threaded surface (32) and the sleeve part (62) has a flange (64) protruding from its front part for fixing, the flange (64) is provided with one or more holes (65) in it. The connector body (12) has a rear limiting surface (18) out of which a stem (75) projects, the stem (75) has a bore hole (77) in its centre line into which a liner (54) for wire guide is fixed, which liner leads in a nest (21) for fitting wire guide conduit end formed on the front surface (15) of the connector body (12), the current transferring body (30) has a pot-shape, having a bottom (39) in which there are openings (41, 42, 43) opening onto the nests (21, 23) formed on the front surface (15), further there is a positioning hole (27) in the side of the connector body (12) in the extension of the threaded bore (37) and the attachment bracket (60) has a conically narrowed part (68) projecting rearwards from the sleeve part (62), and on the inner surface near the end of the narrowed part (68) there is at least one screw thread (72) which The invention relates to a connector (10) for connecting welding torch where the connector comprises a connector body (12) made of electrically insulating material, a cylindrical current transferring body (30) fitted on the cylindrical front part (13) of the connector body (12), made of electrically conductive material, where the current transferring body (30) has a threaded surface (32) and a side contact surface (35) besides the threaded surface (32) on its side surface, a threaded bore (37) on the side contact surface (35) for fixing current cable with screwed joint and a frontal contact surface (33), further an attachment bracket (60), made of electrically insulating plastic, the attachment bracket (60) has a sleeve part (62), which encircled space apart the threaded surface (32) and the sleeve part (62) has a flange (64) protruding from its front part for fixing,—the flange (64) is provided with one or more holes (65) in it. The connector body (12) has a rear limiting surface (18) out of which a stem (75) projects, the stem (75) has a bore hole (77) in its centre line into which a liner (54) for wire guide is fixed, which liner leads in a nest (21) for fitting wire guide conduit end formed on the front surface (15) of the connector body (12), the current transferring body (30) has a pot-shape, having a bottom (39) in which there are openings (41, 42, 43) opening onto the nests (21, 23) formed on the front surface (15), fu

Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure which lowers an effective dielectric constant of the insulator structure. One aspect is a method of forming a low-k insulator structure. In one embodiment, an insulator material is deposited, and a predetermined arrangement of at least one hole is formed in a surface of the insulator material. The insulator material is annealed such that the low-k dielectric material undergoes a surface transformation to transform the arrangement of at least one hole into predetermined arrangement of at least one empty space below the surface of the insulator material. Other aspects are provided herein.

The semiconductor device comprises a lower interconnection part 12 which is formed on a silicon substrate 10 and includes an inter-layer insulation film 36 formed of a low-k film 32and a hydrophilic insulation film 34 formed on the low-k film 32, and an interconnection layer 44a, 44b buried in interconnection trenches 38a, 38b formed in the inter-layer insulation film 36 and having an interconnection pitch which is a first pitch; and an intermediate interconnection part 14 which is formed on the lower interconnection part 12 and includes an inter-layer insulation film 142 formed of low-k films 136, 140, an interconnection layer 152a, 152b buried in interconnection trenches 146a, 146b formed in the inter-layer insulation film 142 and having an interconnection pitch which is a second pitch larger than the first pitch, and an SiC film 154 formed directly on the low-k film 140 and the interconnection layer 152a, 152b.