46results about How to "High resistance state" patented technology

Under one aspect, a memory array includes word lines; bit lines; memory cells; and a memory operation circuit. Each memory cell responds to electrical stimulus on a word line and on a bit line and includes: a two-terminal non-volatile nanotube switching device having first and second terminals, a semiconductor diode element, and a nanotube fabric article capable of multiple resistance states. The semiconductor diode and nanotube article are between and in electrical communication with the first and second terminals, which are coupled to the word line bit line respectively. The operation circuit selects cells by activating bit and/or word lines, detects a resistance state of the nanotube fabric article of a selected memory cell, and adjusts electrical stimulus applied to the cell to controllably induce a selected resistance state in the nanotube fabric article. The selected resistance state corresponds to an informational state of the memory cell.

In at least one embodiment, an electronic system includes a controller, and the controller provides compatibility between an electronic light source and a trailing edge dimmer. In at least one embodiment, the controller is capable of predicting an estimated occurrence of a trailing edge of a phase cut AC voltage and accelerating a transition of the phase cut AC voltage from the trailing edge to a predetermined voltage threshold. In at least one embodiment, the controller predicts an estimated occurrence of the trailing edge of the phase cut AC voltage on the basis of actual observations from one or more previous cycles of the phase cut AC voltage.

A magnetic memory device comprises a magnetic tunnel junction (MTJ) connecting to a bit line to a sense line through an isolation transistor. The MTJ includes a ferromagnetic layer having a magnetic hard axis. An assist current line overlies the bit line and is insulated from the bit line. The MTJ is switchable between a first, relatively high resistance state and a second, relatively low resistance state. The assist current line applies a magnetic field along the magnetic hard axis in the ferromagnetic layer, independently of current flow through the MTJ for assisting switching of the MTJ between the first and second states.

A non-volatile resistive switching memory that includes a material which changes between the insulative and conductive states. The material is stabilized against charge trapping by oxygen vacancies by an extrinsic ligand, such as carbon.

A memory device 10 has an arrangement in which a memory thin film 4 is sandwiched between first and second electrodes 2 and 6, the memory thin film 6 contains at least rare earth elements, the memory thin film 4 or a layer 3 in contact with the memory thin film 4 contains any one of elements selected from Cu, Ag, Zn and the memory thin film 4 or the layer 3 in contact with the memory thin film 4 contains any one of elements selected from Te, S, Se. The memory device can record and read information with ease stably, and this memory device can be manufactured easily by a relatively simple manufacturing method.

This disclosure describes techniques for generating physically unclonable functions (PUF) from non-volatile memory cells. The PUFs leverage resistance variations in non-volatile memory cells. Resistance variations in array of non-volatile memory cells may be produce a bitstring during an enrollment process. The bitstring may be stored in the non-volatile memory array. Regeneration may include retrieving the bitstring from the non-volatile memory array.

A physical unclonable function (PUF) device consisting of a hybrid CMOS-memristor circuit that leverages variations in the required write-time of a memristor. Variations in the time required to write, or SET, a memristor from a high to low resistance state arise from variability in physical parameters such as the memristor thickness. When applying a SET voltage across the memristor for the nominal minimum SET time, variability leads to a situation where the memristor will actually SET to the low resistance state only 50% of the time. When the device does not SET it will remain in the high resistance state. Since the to resistance state of the memristor corresponds to reading either a logic 1 or logic 0 on the output of the circuit, the write-time based memristive PUF produces a digital signature directly corresponding to the fabrication process-induced physical variations of an integrated circuit.

A MRAM includes a first magnetoresistive effect (MR) element that takes a low and high resistance states. A second MR element is fixed to a low or high resistance state. First and second MOSFETs are connected to the first and second MR elements, respectively. A sense amplifier amplifies a difference between values of current flowing through the first and second MOSFETs. A current circuit outputs reference current whose value lies between current flowing through the first MR element of the low and high resistance states. A third MOSFET has one end that receives the reference current and is connected to its own gate terminal. The gate terminal of the second MOSFET receives the same potential as the gate terminal of the third MOSFET. A first resistance element is connected to the others end of the third MOSFET and has the same resistance as the second magnetoresistive effect element.

A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. High and low resistance states of the MRLC occurs based on the relative magnetization orientations of SRL and CFL. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. A voltage-induced switching principle can be used with MRLC embodiments of the present invention to switch the SRL to parallel or anti-parallel with respect to the magnetization CFL in both perpendicular and in-plane anisotropy embodiments.

The invention relates to the technical field of flexible electronic devices, in particular to an inorganic flexible resistive memory and a preparation method thereof. The inorganic flexible resistivememory has better bending characteristics, the high resistance state and low resistance state of the device are relatively stable under different bending radii and bending times, and the influence ofbending deformation on the storage performance of the functional layer material can be effectively alleviated. The inorganic flexible resistive memory has large switching ratio, low setting voltage and no Forming process and can ensure the normal operation of the device and meet the requirements of low power consumption. The inorganic flexible resistive memory has good thermal stability, the highand low resistance states of the device can be kept stable for about 105s under the condition of 85 DEG C, and the ratio of the high and low resistance states of the device is still above 102 after 107 consecutive switching operations in the pulse mode, which can ensure the normal operation of the device without misreading.

Provided are a non-volatile memory device and a method of operating the non-volatile memory device. The non-volatile memory device includes a switching device and a storage node connected to the switching device, wherein the storage node comprises: a first electrode connected to the switching device; a chalcogenide material layer formed on the first electrode; and a second electrode formed on the chalcogenide material layer, and one of the first and second electrodes comprises an electrode contact layer formed adjacent to a limited region of the chalcogenide material layer, and a property of the electrode region adjacent to the chalcogenide material layer is changed reversibly according to the direction in which a current is applied, thereby changing between a high resistance state and a low resistance state.

The invention discloses a moving target detection circuit based on a memristor and a CMOS. The moving target detection circuit comprises an adjacent frame difference comparison module and a signal processing module connected in order; the adjacent frame difference comparison module receives external video data and is used for difference comparison of high 4-bit numerical values on various pixel points between adjacent two frame images; the signal processing module is used for acquiring binary output corresponding to various pixel points after orderly performing current-voltage signal conversion, weighted sum and threshold comparison on the difference comparison result output by adjacent frame difference comparison module, thereby generating a white-black image for describing the moving target contour. The difference comparison is performed on the signal from an image sensor through a mixed structure array of the memristor and the CMOS. The detection circuit has the advantages of beingsimple in structure, small in volume, strong in extensibility and low in power consumption, the contour detection on the moving target can be accomplished on a hardware circuit, and the data processing pressure of the computer can be shared, thereby laying the foundation for realizing higher-order image processing task.

The invention relates to a cobalt oxide film of interrupted oxide material, which is in a polycrystal state and has a chemical formula of Co3O4 and a thickness of 200nm. The preparation method comprises the following steps: (1), preparing ceramic target material of CoOx (x is larger than 0 and less than 4/3); (2), fixing the target material of CoOx on a target, fixing a substrate on a substrate platform and arranging the target and the substrate platform in a growth chamber; (3), vacuumizing the growth chamber by a mechanical pump and a molecular pump, closing the mechanical pump, opening an inlet valve and pumping oxygen to the growth chamber until oxygen pressure is 20Pa; (4), focusing laser beams of a laser on the target material of CoOx by a lens; (5), heating the substrate platform by a resistance furnace so that the temperature of the substrate reaches a temperature of 660 DEG C; and (6), confirming sedimentation time according to single-pulse energy to sedimentate the film of Co3O4 with the thickness of 200nm on the substrate. The film is used to prepare a nonvolatile interrupted memory storage element which adopts a sandwich structure as a basic configuration, i.e., a polycrystal oxide film of Co3O4 is sedimentated on a Pt electrode film of a lower electrode, and a Pt probe is used as an upper electrode to form a memory unit.

A method of printing an electrode component is disclosed. The method can include steps of electrostatically printing a polymer onto a substrate, where at least a portion of the printing occurs while the polymer is in a first conductive state, and altering the polymer to a second conductive state that is more conductive than the first conductive state, thereby forming the electronic component.

A method for deactivating memory cells affected by the presence of grain boundaries in polycrystalline selection devices includes crystallizing a semiconductor layer in a diode stack to form a polycrystalline layer for selection diodes formed in a crossbar array. To achieve a crystalline state in phase change memory elements coupled to corresponding selection diodes perform an anneal. Memory cells having shunted selection diodes due to grain boundaries are identified by scanning the array using sense voltages. A second voltage larger than the sense voltages is applied to the phase change memory elements gated by the shunted selection diodes such that the phase change memory elements gated by the shunted diodes achieve a permanently high resistive state.

The present invention relates to a nonvolatile memory device and to a method for manufacturing same. According to the present invention, the blocking insulation layer of a nonvolatile memory device having a typical SONOS structure is replaced with a threshold voltage switching material, which changes to a low resistance state only while a voltage greater than a threshold voltage is applied while maintaining a high resistance state under normal conditions and returning to the high resistance state when the applied voltage is removed. The present invention performs a program operation by injecting charges from a gate electrode layer into a charge trap layer through an insulation layer formed of the threshold voltage switching material after applying a voltage pulse greater than the threshold voltage to the gate electrode layer.