63results about How to "Eliminate capacitance" patented technology

A page buffer of a non-volatile memory device and a method for programming and reading the same is provided. The page buffer includes a first latch unit and one or more second latch units for storing data, transfer units connected between the first latch unit and the second latch units for transferring the data stored in the first latch unit to the second latch units, a path select unit that that senses data from bit lines and stores the sensed data in the first latch unit, and, in a program operation, transfers the data from the first and second latch units to the bit lines, a sensing unit for allowing the path select unit to sense data or the data received from the bit lines to be stored in the first latch unit, and a data I / O unit.

The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.

A process for manufacturing a Junction Field-Effect Transistor, comprises doping a semiconductor material formed on an insulating substrate with impurities of a first conductivity type to form a well region. The process continues by implanting impurities of a second conductivity type into said well region to form a channel region, and by implanting impurities of the first conductivity type in said well region to form a back gate region. The process continues by forming a trench to expose at least one sidewall of said channel region, wherein the trench extends far enough along the sidewall to expose at least a portion of said back gate region. The process continues by depositing polysilicon to fill said trench along the at least one sidewall of said channel region and at least a portion of said back gate region, wherein at least a portion of the polysilicon will form a gate contact. The polysilicon is then doped with impurities of a first conductivity type. The process concludes by annealing the polysilicon to activate the doped impurities and to cause the doped impurities to diffuse along the at least one sidewall of said channel region so as to form a top gate region. The top gate region extends far enough to make electrical contact with said back gate region.

The transistor includes an emitter region 17 disposed in a first isolating well 11, 150 formed in a semiconductor bulk. An extrinsic collector region 16 is disposed in a second isolating well 3, 150 formed in the semiconductor bulk SB and separated laterally from the first well by a bulk separator area 20. An intrinsic collector region is situated in the bulk separator area 20 in contact with the extrinsic collector region. An intrinsic base region 100 is formed which is thinner laterally than vertically and in contact with the intrinsic collector region and in contact with the emitter region through bearing on a vertical flank of the first isolating well facing a vertical flank of the second isolating well. An extrinsic base region 60 is formed which is substantially perpendicular to the intrinsic base region in the top part of the bulk separator area, and contact terminals C, B, E respectively in contact with the extrinsic collector region, the extrinsic base region, and the emitter region.

A conductivity counter and method of determining conductivity of a fluid sample are disclosed. The counter is suitable for high-speed, accurate counting of discrete events or items, such as cancer cells, passing through a fluid sample cell. A variable frequency current source is used to supply an excitation current to a sample cell connected in parallel with an inductance or the electrical equivalence of an inductance. This configuration can be accurately modeled as a parallel RLC circuit when the system is operated at a stable frequency. The current source frequency is tuned to the resonance frequency of the equivalent RLC circuit, which effectively eliminates the capacitive and inductive components of the impedance, leaving only purely resistive components. The output of the equivalent RLC circuit is connected to a high input impedance buffer amplifier and then to a phase sensitive detector, which detects the phase shift resulting from the equivalent RLC circuit. The output is filtered and a differencing amplifier is used to zero out the output signal due to the system components and the sample cell buffer solution prior to taking active readings. The remaining output signal is due to perturbations in the fluid sample, such as passing cancer cells. This output is sent to a high-gain output amplifier and then supplied to a suitable signal processing device or system, such as a computer.

A Junction Field-Effect transistor with no surface contact for the back gate and twice as much transconductance in the channel and with a higher switching speed is achieved by intentionally shorting the channel-well PN junction with the gate region. This is achieved by intentionally etching away field oxide outside the active area at least in the gate region so as to expose the sidewalls of the active area down to the channel-well PN junction or a buried gate which is in electrical contact with the well. Polysilicon is then deposited in the trench and doped heavily and an anneal step is used to drive impurities into the top and sidewalls of the channel region thereby creating a “wrap-around” gate region which reaches down the sidewalls of the channel region to the channel-well PN junction. This causes the bias applied to the gate terminal to also be applied to the well thereby modulating the channel transconductance with the depletion regions around both the gate-channel PN junction and the channel-well PN junction.

The present invention is an apparatus and system for reducing bondpad capacitance of an integrated circuit. Circuitry of the present invention may produce a negative capacitance approximately equal in magnitude to the capacitance associated with the bondpad and thereby effectively eliminate the bondpad capacitance. Values of the components of the circuitry may be selectively and independently chosen to synthesize a variable range of negative capacitance and thus produce a negative capacitance approximately equal in magnitude to a unique capacitance associated with the bondpad of a variety of integrated circuits.