87results about How to "High-frequency operation" patented technology

A wireless communications system optimizes performance by dividing communications functionality between a wireless pacemaker and a wireless monitoring base station according to the design constraints imposed by the system elements. Typical design constraints include high frequency operation, low pacemaker power consumption, reasonable range, high data rate, minimal RF radiation of internal circuitry, small pacemaker antenna system, simple pacemaker RF circuit design, high reliability, low pacemaker cost, and use of existing pacemaker construction methodologies.

Pressure swing adsorption (PSA) separation of a feed gas mixture is performed within an apparatus having typically a single prime mover powering a feed compressor for one or multiple rotary PSA modules in parallel, each module including a rotor with a large number of angularly spaced adsorber elements, with valve surfaces between the rotor and a stator so that individual adsorber elements are opened to compartments for staged pressurization and blowdown, with thermally boosted energy recovery from staged expansion of countercurrent blowdown and light reflux gases, and a plurality of adsorber elements opened at any instant to each compartment so that each compressor and expander stage operates under substantially steady conditions of flow and pressure.

The present invention provides a thin film write head having an improved laminated flux carrying structure and method of fabrication. The preferred embodiment provides laminated layers of: high moment magnetic material, and easily aligned high resistivity magnetic material. In the preferred embodiment, the easily aligned laminating layer induces uniaxial anisotropy, by exchange coupling, to improve uniaxial anisotropy in the high moment material. This allows deposition induced uniaxial anisotropy by DC magnetron sputtering and also provides improved post deposition annealing, if desired. It is preferred to laminate FeXN, such as FeRhN, or other crystalline structure material, with an amorphous alloy material, preferably Co based, such as CoZrCr. In the preferred embodiment, upper and lower pole structures may both be laminated as discussed above. Such laminated structures have higher Bs than structures with insulative laminates, and yokes and pole tips and may be integrally formed, if desired, because flux may travel along or across the laminating layers. The preferred embodiment of the present invention improves soft magnetic properties, reduces eddy currents, improves hard axis alignment while not deleteriously affecting the coercivity, permeability, and magnetostriction of the structure, thus allowing for improved high frequency operation.

Pressure swing adsorption separation of a feed gas mixture, to obtain a purified product gas of the less strongly adsorbed fraction of the feed gas mixture, is performed with a cooperating set of "N" adsorbers in a rotary assembly, with each adsorber communicating at its product end directly to a rotary cyclic displacement chamber, and at its feed end by rotary distributor valve ports to a rotary piston feed compressor and a rotary piston exhaust vacuum pump. The compressor and vacuum pump are integrated with the cycle, and rotate at "N" times the cycle frequency. Alternative adsorber configurations for high frequency operation are disclosed.

An efficient and flexible current-mode driver delivers power to one or more light sources in a backlight system. In one application, the current-mode driver is configured as an inverter with an input current regulator, a non-resonant polarity-switching network, and a closely-coupled output transformer. The input current regulator can output a regulated current source in a variety of programmable wave shapes. The current-mode driver may further include a rectifier circuit and a second polarity-switching network between the closely-coupled output transformer and a lamp load. In another application, the current-mode driver delivers power to a plurality of light sources in substantially one polarity by providing a regulated current to a network of time-sharing semiconductor switches coupled in series with different light sources coupled across each semiconductor switch.

A high-frequency BGA device (500) with the chip (501) assembled by metal bumps (503) on an insulating substrate (502) with conductive vias (505) and metal traces (504). Chip bumps which serve the high frequency signal terminals are attached directly to the lands (510) on the vias in order to minimize parasitic electrical parameters such as inductance, resistance, and IR drops, thus achieving the required 0.1 nH inductance for each chip terminal. Chip bumps which serve the remaining chip terminals are attached to pads on certain substrate traces. In both cases, the bumps can be attached reliably because the lands on the vias and the pads on the traces are plated with additional metal layers (511, 512), which provide extra thickness as well as a metallurgically suitable surface.

An oscillator system is disclosed and includes an oscillator circuit having a differential output producing a differential output signal thereat having a frequency that is a function of an input voltage. The oscillator system further includes an output buffer coupled to the differential output of the oscillator circuit. The output buffer includes an inductive voltage divider circuit configured to weaken a loading at the oscillator differential output and it increases the output power.

A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps. In order to solve the problem, according to the present invention, there is provided a clocked inverter including a first transistor and a second transistor connected in series, and a compensation circuit including a third transistor and a fourth transistor connected in series. In the clocked inverter, gates of the third transistor and the fourth transistor are connected to each other, drains of the third transistor and the fourth transistor are each connected to a gate of the first transistor, sources of the first transistor and the fourth transistor are each electrically connected to a first power source, a source of the second transistor is electrically connected to a second power source, and an amplitude of a signal inputted to a source of the third transistor is smaller than a potential difference between the first power source and the second power source.

The present invention provides a shift register which can operate favorably without providing a level shift portion. The first clocked inverter at the (2n−1)-th stage operates in accordance with the first output from the previous stage, an output from the second clocked inverter at the previous stage, and the first CK signal; the second clocked inverter at the (2n−1)-th stage operates in accordance with the second output from the previous stage, an output of the first clocked inverter at the (2n−1)-th stage, and the first CK signal; one of the first output and the second output is equal to a potential of VDD and the other is equal to a potential of VSS; the first CK signal at the 2n-th stage operates the third output from the (2n−1)-th stage, an output of the second clocked inverter and the second CK signal; the second clocked inverter at the 2n-th stage operates in accordance with the fourth output from the (2n−1)-th stage, an output from the first clocked inverter at the 2n-th stage, and the second CK signal; one of the third output and the fourth output is equal to the potential of VDD and the other is equal to the potential of VSS, and the second CK signal is an inversion signal of the first CK signal and the amplitude of the CK signal is smaller than the power supply potential.

An output buffer is disclosed and includes a differential output buffer input configured for coupling to a differential output of an input circuit. The output buffer further includes an inductive voltage divider circuit coupled to the differential output buffer input, and configured to weaken a loading at the differential output of the input circuit.

In a memory module, reference potential connecting patterns are disposed on high frequency signal lines and/or on the extension lines extending from the terminal ends of the signal lines as well as a shield cover for covering semiconductor memory chips is disposed on the substrate, and the reference potential connecting patterns are connected to the shield cover through metal cover contact parts.