170 results about "Voltage noise" patented technology

A system and method of characterizing a device under test wherein a signal is injected into the device under test, the response to the injected signal is measured to determine the impedance of the device under test in the frequency domain, the impedance is converted to the time domain, and the voltage noise of the device under test is calculated based on the impedance of the device under test in the time domain.

One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes an interposer, which is configured to be sandwiched between the IC device and a circuit board. This interposer has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the interposer and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

A semiconductor power network (100) decoupling capacitance (decap) budgeting problem is co-optimized with a wiring enhancement problem, wherein the solution is formulated to minimize the total decap to be added or wiring changes (addition of wires (420)) to be made to the network (100). Voltage constraints, available white space and other constraints determine the amount of decap to be added. Wire enhancements and / or added decap can be distributed throughout a violation region (120) of the semiconductor circuit (100) design to reduce dynamic supply voltage noise so that dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level (220).

An objective is to provide a multilayer filter capable of preventing an electric current rapidly flowing by virtue of varistor effect, from passing as noise, upon application of noise of a high voltage over a varistor voltage to its input. A multilayer filter has an inductor part 10 and a varistor part 20 in a laminate 2, and the inductor part 10 has the DC resistance of 4 Ω-100 Ω. This prevents an electric current rapidly flowing by virtue of the varistor effect, from passing as noise, upon application of noise of a high voltage over the varistor voltage to the input.

A semiconductor circuit is provided in which no error signal is generated even when the circuit is exposed to a transient voltage noise that occurs with a transition from a first state indicating a conduction of a high-potential side switching device to a second state indicating a non-conduction of the high potential side switching device, or vice versa. A high potential switching device drive circuit 1 includes short circuit devices 31 and 32 that are controlled by the second level shifted signals S6 and S7 simultaneously generated across the second load resistances 30 and 29, respectively, to thereby serving to prevent a signal from being generated at one of the output sections where the other one of the first level shifted signals S4 and S5 is to be generated, when either one of the first shifted signals S4 and S5 in level shift circuit ON and OFF sections is generated across first load resistance 28 or 27 in a level shift circuit 2.

A high-frequency device includes an antenna terminal, a signal line connected to the antenna terminal, a high-frequency signal processing circuit connected to the signal line, a capacitance element having one end connected to the signal line and other end grounded, and an inductor having one end connected to the signal line and other end grounded. The high-frequency device can protect the high-frequency signal processing circuit from a high voltage noise, such as a static electricity, having a frequency close to a signal pass band.

One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes a package which is configured to be sandwiched between the IC device and a circuit board. This package has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the package and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

The invention discloses a power distribution network line-transformer relationship anomaly identification and judgment method, which comprises the following steps of distribution transformer voltage noise processing based on abnormal value detection, voltage acquisition point waveform curve stability calculation based on a sliding window algorithm, three-phase imbalance neutral point offset reduction based on a reduction method, a Pearson-correlation-coefficient-based voltage curve calculation method for judging the similarity degree of voltage curves, topological anomaly clustering based on ahierarchical clustering method, and fault determination. On the basis of massive operation data of a centralized power grid, the operation situation of a topological structure is reflected by researching and utilizing service characteristics of voltage waveform similarity through a distribution transformer voltage waveform hierarchical clustering method, and a standing book and power grid topological data are accurately identified; on the basis of a voltage curve waveform correlation coefficient, hierarchical clustering is used to realize accurate identification of the topological structure,and the accuracy and authenticity of the topological structure of the power distribution network are comprehensively improved; and through secondary comparison, the fault type is quickly determined.

One embodiment of the present invention provides capacitive decoupling on the surface of a semiconductor die, instead of providing the decoupling on a package or printed circuit board to which the semiconductor die is attached. In this embodiment, a surface of a semiconductor die includes exposed power and ground conductors, which are electrically coupled to internal power and ground nodes within the semiconductor die. To provide the wafer-level decoupling, a plurality of bypass capacitors are electrically coupled between pairs of exposed power and ground conductors, so that the plurality of bypass capacitors reduce voltage noise between the power and ground conductors on the semiconductor die.

Time-resolved emission can be used to measure loop-synchronous, small-signal voltage perturbation in integrated circuits. In this technique the measurements are completely non-invasive and so reflect the true device behavior. The time-dependant propagation delay caused by Vdd modulation also shows the expected qualitative signature. This technique should find applications in circuits with relatively fast clock-like circuits where loop-synchronous voltage pickup is limiting circuit behavior.