33 results about "Sparse matrix-vector multiplication" patented technology

Techniques for optimizing sparse matrix-vector multiplication (SpMV) on a graphics processing unit (GPU) are provided. The techniques include receiving a sparse matrix-vector multiplication, analyzing the sparse matrix-vector multiplication to identify one or more optimizations, wherein analyzing the sparse matrix-vector multiplication to identify one or more optimizations comprises analyzing a non-zero pattern for one or more optimizations and determining whether the sparse matrix-vector multiplication is to be reused across computation, optimizing the sparse matrix-vector multiplication, wherein optimizing the sparse matrix-vector multiplication comprises optimizing global memory access, optimizing shared memory access and exploiting reuse and parallelism, and outputting an optimized sparse matrix-vector multiplication.

The invention relates to a prediction method and system for vector multiplication operation time of a sparse matrix, and the method comprises the following steps: constructing a convolutional neural network which comprises an input layer, a feature processing layer, a data splicing layer and an output layer, wherein the input layer is used for inputting the characteristics of a row characteristicmatrix, the characteristics of a column characteristic matrix and the characteristics of an architecture parameter extension matrix in a sparse matrix; the feature processing layer is used for extracting features in the previous layer; the data splicing layer is used for splicing the extracted features of the row feature matrix, the extracted features of the column feature matrix and the extractedfeatures of the architecture parameter extension matrix; the output layer is used for outputting a prediction result and obtaining a plurality of groups of sparse matrixes with known sparse matrix vector multiplication operation time as sample data, and inputting the sample data into the convolutional neural network to realize training of the convolutional neural network; and inputting a sparse matrix to be classified into the trained convolutional neural network to realize prediction of sparse matrix vector multiplication operation time.

Systems and methods are provided for sparse matrix vector multiplication with a matrix vector multiplication unit. The method includes partitioning a sparse matrix of entries into a plurality of sub-matrices; mapping each of the sub-matrices to one of a plurality of respective matrix vector multiplication engines; partitioning an input vector into a plurality of sub-vectors; computing, via each matrix vector multiplication engine, a plurality of intermediate result vectors each resulting from a multiplication of one of the sub-matrices and one of the sub-vectors; for each set of rows of the sparse matrix, adding elementwise the intermediate result vectors to produce a plurality of result sub-vectors; and concatenating the result sub-vectors to form a result vector.

The invention discloses an encoder of an LDPC code with a layered quasi-cyclic extension structure, comprising: an input buffer, a first processing-buffering pipeline stage, a second processing pipeline stage, a third buffering pipeline stage, and a fourth processing-buffering pipeline stage and output stage, according to the characteristic that the parity check matrix H is a quasi-cyclic shift matrix splicing, the pipeline structure of the RU coding method is simplified, the number of pipeline stages is reduced from six to four, and the coding delay is shortened. At the same time, according to the implementation characteristics of the main functional modules, the maximum pipeline delay is reduced and the encoding throughput is improved. Then, according to the characteristics of the quasi-cyclic shift matrix operation, the resource consumption of the encoder ROM was reduced, and the sparse matrix multiplication vector in the RU method was replaced by the quasi-cyclic shift unit matrix multiplication vector, and the quasi-cyclic shift matrix multiplication vector was used instead of Non-sparse matrix-by-vector in RU methods. In order to meet the requirements of variable code length and variable code rate, the ping-pong RAM between stages can reserve a large storage space.

A processor for sparse matrix calculation can include an on-chip memory, a cache, a gather / scatter engine and a core. The on-chip memory can be configured to store a first matrix or vector, and the cache can be configured to store a compressed sparse second matrix data structure. The compressed sparse second matrix data structure can include: a value array including non-zero element values of the sparse second matrix, where each entry includes a given number of element values; and a column index array where each entry includes the given number of offsets matching the value array. The gather / scatter engine can be configured to gather element values of the first matrix or vector using the column index array of the sparse second matrix. In a horizontal implementation, the gather / scatter engine can be configured to gather sets of element values from different sub-banks within a same row based on the column index array of the sparse matrix. In a vertical implementation, the gather / scatter engine can be configured to gather sets of element values from different rows based on the column index array of the sparse matrix. In a hybrid horizontal / vertical implementation, the gather / scatter engine can be configured to gather sets of element values from sets of rows and from different sub-banks within the same rows based on the column index array of the sparse matrix. The core can be configured to perform sparse matrix-matrix multiplication or sparse-matrix-vector multiplication using the gathered elements of the first matrix or vector and the value array of the compressed sparse second matrix.

The invention discloses a method for realizing heterogeneous many-core of sparse matrix-vector multiplication based on domestic SW26010 processors. As the non-zero elements of a sparse matrix are distributed very irregularly, two different static and dynamic task partitioning methods are designed in the method, so as to adapt to different sparse matrices; a set of dynamic and static cache mechanism is provided, so as to promote the memory access hit rate of a vector x; a set of self-adapting optimization method is provided, specific to the sparse matrix, the optimal execution parameters can be dynamically selected, so as to promote the running performance. According to the method disclosed by the invention, 16 sparse matrices in a Matrix Market matrix set are adopted to conduct test, the running edition SpMV has about 10 times of acceleration to the utmost extent compared with the single main core of a domestic SW processor, and the average speed-up ratio is 6.51.

The invention relates to a sparse matrix-vector multiplication calculation unit for arranged block diagonal weight matrices, comprising: several processing units and an accumulator; the output of the processing unit is connected to the accumulator. The sparse matrix-vector multiplication calculation unit for arranged block diagonal weight matrices provided by the present invention makes full use of the sparseness of the weight matrix after pruning, and avoids multiplication operations between zero-value weights and corresponding input excitation elements. Zero-hopping operations can be dynamically enabled in conjunction with sparsity of input stimuli. The sparsity of the intermediate product obtained by multiplying the weight and the corresponding input stimulus is fully utilized, and the accumulation operation between the zero value product and the corresponding product is avoided. The designed pointer generator eliminates the storage overhead of the pointers that record the location information of non-zero values.