Parallel computing method for sparse matrix vector multiplication of Shenwei architecture

Abstract

The present invention relates to a parallel computing method for sparse matrix vector multiplication of a Shenwei architecture. The method comprises: dividing a sparse matrix from an original single-level data structure into a multi-level data structure, wherein the multi-level data structure comprises four levels of fleet, block, tile, and slice; and corresponding the multi-level data structure to a Shenwei hardware architecture and the calculation hierarchy. According to the method disclosed by the present invention, the spatial and temporal locality of the data is improved, and the number of times of interactions between the core group and the memory is reduced.

Description

technical field [0001] The invention relates to the field of high-performance computers, in particular to a parallel computing optimization method for multiplying sparse matrices and dense vectors applicable to the Sunway supercomputer architecture. Background technique [0002] The multiplication of sparse matrix and dense vector (Sparse Matrix-vector Multiply, abbreviated as SpMV) is a very important but independent computing core in many domain programs. It has a wide range of applications in many fields involving high performance computing, such as fluid mechanics and molecular dynamics. Moreover, problems in the field of graph computing such as PageRank and breadth-first search can also be abstracted into SpMV problems. [0003] The SpMV problem has two prominent problems in the calculation process, namely the irregularity of the calculation and memory access modes. These irregularities are caused by the randomness of the memory access order, and it is difficult to ta...

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Problems solved by technology

These irregularities are due to the randomness of the memory access order, and it is difficult to take advantage of the locality of the data

Since this irregular pattern has a lot to do with the random order of the input sparse matrix, it is difficult to solve it at the compiler stage

From a hardware point of view, these irregularities can lead to hidden write conflicts, which affect and limit parallelism at the instruction level and thread level.

[0004] These make the SpMV algorithm applied to the Sunway supercomputer architecture to bring greater challenges

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