141 results about "Signal Width" patented technology

Multilayer high speed flex printed circuit boards (FLEX-PCBs) are disclosed including a dielectrics systems with the back-side trenches, adhesives, signal lines and ground planes, wherein the signal line and ground plane lane are located on the dielectrics. Using of the open trenches in the substrate help to reduce the microwave loss and dielectric constant and thus increasing the signal carrying speed of the interconnects. Thus, according to the present invention, it is possible to provide a simply constructed multiplayer high speed FLEX-PCB using the conventional material and conventional FLEX-PCB manufacturing which facilitates the design of circuits with controlled bandwidth based on the trench opening in the dielectrics, and affords excellent connection reliability. As the effective dielectric constant is reduced, the signal width is required to make wider or the dielectric thickness is required to make thinner keeping fixed characteristics impedance. The fundamental techniques disclosed here can also be used for high-speed packaging.

The present invention relates to a method of circuit verification in digital design and in particular, relates to a method of register transfer level property checking to enable the same. Today's electrical circuit designs frequently contain up to several million transistors, and circuit designs need to be checked to ensure that circuits operate correctly. Formal methods for verification are becoming increasingly attractive since they confirm design behavior without exhausting simulating a design. A digital circuit design verification method, prior to a property checking process for each property of a non-reduced RTL model, determines a reduced RTL model which retains specific signal properties of a non-reduced RTL model which are to be checked. A linear signal width reduction causes an exponential reduction of the induced state space. Reducing state space sizes in general goes hand in hand with reduced verification runtimes, thus speeding up verification tasks.

The present invention relates to a method of circuit verification in digital design and in particular relates to a method of register transfer level property checking to enable the same. Today's electrical circuit designs frequently contain up to several million transistors and circuit designs need to be checked to ensure that circuits operate correctly. Formal methods for verification are becoming increasingly attractive since they confirm design behavior without exhaustively simulating a design. The present invention provides a digital circuit design verification method wherein, prior to a property checking process for each property of a non-reduced RTL model, a reduced RTL model is determined, which reduced RTL model retains specific signal properties of a non-reduced RTL model which are to be checked. A linear signal width reduction causes an exponential reduction of the induced state space. Reducing state space sizes in general goes hand in hand with reduced verification runtimes, and thus speeding up verification tasks.

The invention provides an active clamp flyback converter self-adaptive control method and circuit, which are used for controlling a conduction time of a clamper tube. The active clamp flyback converter self-adaptive control method and circuit have the following characteristics and effects: a multiplexing auxiliary winding voltage sampling pin determines whether a main switch pipe ZVS is switched on or not, and no additional pin is needed, so that the encapsulation size is reduced; a switch node voltage proportional value in the conduction period of the main switch pipe is saved, and the conduction realization situation of ZVS is determined cycle by cycle on a rising edge of a main switch pipe driving signal, so that the self adaption can be actually realized; since the saved switch node voltage proportional value is gradually updated cycle by cycle, the determination result of the conduction realization situation of the main switch pipe ZVS is not influenced by the device precision, and the determination result is more accurate; and by virtue of the bidirectional control for the width of the clamper pipe driving signal, on the premise of realizing the conduction of the main switchpipe ZVS, the negative current flowing by a diode of the main switch pipe body can be reduced as far as possible, and the loss can be reduced.

High speed flex printed circuit boards (FLEX-PCBs) are disclosed comprising a dielectrics systems with the back-side trenches, adhesives, signal lines and ground-plans, wherein the signal line and ground-plan are located on the dielectrics. Using of the open trenches in the substrate help to reduce the microwave loss and dielectric constant and thus increasing the signal carrying speed of the interconnects. Thus, according to the present invention, it is possible to provide a simply constructed high speed FLEX-PCB using the conventional material and conventional FLEX-PCB manufacturing which facilitates the design of circuits with controlled bandwidth based on the trench opening in the dielectrics, and affords excellent connection reliability. As the effective dielectric constant is reduced, the signal width is required to make wider or the dielectric thickness is required to make thinner keeping fixed characteristics impedance. The fundamental techniques disclosed here can also be used for high-speed packaging.

An inverter control device drives one of the two switching circuits with a fixed conduction width and changes the control method of the other switching circuit between pulse-width modulation, phase control method, and drive signal width control method by phase control method according to an output state, to implement highly accurate control at low output while suppressing heat generation of a switching element.

A horizontal scanning period correction value setting circuit compares a video signal representing a display image of pixel formation portions of polarity-inverted lines and a video signal representing a display image of pixel formation portions of the next row, and generates a signal width correction value for correcting the length of the horizontal scanning period. For this, the signal width correction value is set such that the charge ratios of the pixel formation portions are constant, regardless of a difference between a target voltage of the driving video signals when the polarity is inverted and a target voltage of the driving video signals when the polarity is sustained. Then, a source output control signal and a gate output control signal are generated based on the signal width correction value, and the scanning signals and the driving video signals are generated based on the source output control signal and the gate output control signal.

An implantable cardioverter, especially defibrillator, having a morphology detector (3) to measure and evaluate EKG signals for the purpose of discriminating between different tachycardia conditions of the heart. The morphology detector (3) having a signal width detector, by which the respective width of the EKG signal between every two successive crossings through the isoelectrical line of the EKG can be measured; a threshold value discriminator to determine whether the EKG signal between two such successive crossings exceeds a defined threshold value; and a comparator for the signal width, coupled to the signal width detector and the threshold value discriminator. The morphology detector compares the respective current signal width value selected by the threshold value discriminator and measures by signal width detector to a pre-set selection parameter to differentiate between two different conditions of tachycardia.

The invention discloses a laser pulse distance measuring method for correcting a measurement error by utilizing received signal width. The method comprises the following steps that a pulse laser is adopted for a light source, a driving circuit drives the laser to emit narrow-pulse-width laser pulses, and the laser pulses are emitted at a certain beam-divergence angle after being shaped by a transmitting optical system. Target echo signals are converged on the photosensitive surface of a photoelectric detector through a receiving optical system to achieve photoelectric conversion. Electric signals are converted into digital signals after being preprocessed. An FPGA phase-shifting clock is used for carrying out high-speed sampling on echoes, and the time delay and the receiving signal widthof the reflected echoes are measured. A data table is made according to the relation curve of actually measured received signal width and the delay compensation amount. A distance measuring machine isused for obtaining time identification errors so as to correct a distance measuring result through a table look-up mode according to the leading edge time and the received signal width measured by the FPGA. According to the invention, higher distance measuring precision can be realized, and the method has a good application prospect in the relevant field of laser distance measuring.

A circuit for controlling an AC-timing parameter of a semiconductor memory device and method thereof are provided. The AC-timing parameter control circuit includes a delay-time-defining portion, a comparing portion, and a controlling portion. The control circuit compares the pulse width or period of an input signal to one or more different reference-widths pulses, with the reference width(s) set by the delay-time-defining portion and the reference pulses generated by the comparing portion. The controlling portion indicates whether the input signal width or period was less than or greater than each o the reference-width pulses. The control circuit output signals can be used to tailor the operation of the device based on a direct comparison of an AC-timing parameter to one or more reference values.

The invention discloses a decoder suitable for PIE coding, which relates to the technical field of radio-frequency identification (RFID). The decoder comprises a Cnt_RTcal counter, a Cnt_even counter, a Cnt_odd counter, a Cnt_ctrl counter, a Mux multiway selector, a comparator and three D triggers. The Cnt_RTcal counter counts the time length of the forward link calibration code RTcal, and the Cnt_ctrl counter counts the number of the falling edges in the PIE coded data frame received by the tag. The counting output Cnt_ctrl of the Cnt_ctrl counter controls the Cnt_odd counter and the Cnt_even counter to respectively and alternately count the signal width between every two adjacent falling edges of the PIE code signal. The invention can overcome the effect of jittering and frequency shifting along with temperature, voltage and the like of a receiving clock, thereby ensuring the stable synchronous reception of the PIE coding and reducing the power consumption of the PIE coding processing circuit. The invention has the characteristics of small size, economy and convenience.

Disclosed are an inverter control device and an inverter control method, wherein a switching circuit on one side is driven with a fixed conduction width and a switching circuit on the other side is switched to a pulse width modulation system, a phase control system, or a drive signal width control system using the phase control system according to the output state, thereby implementing high accurate control at the time of small output while suppressing the heat generation of switching elements.

Methods for establishing modulator timing for a QKD system (100) having QKD stations (Alice, Bob) with respective modulators (MA, MB) are disclosed. The timing method includes exchanging non-quantum signals (P1, P2) between the two QKD stations and performing respective coarse timing adjustments by scanning the modulator timing domain with relatively coarse timing intervals (ΔT1C, ΔT2C,) and wide (coarse) modulator voltage signals (W1C, W2C). Coarse timings (T1C, T2C) are established by observing a change in detector counts between single-photon detectors (32a, 32b) when modulation occurs in exchanged non-quantum signals. The method also includes performing a fine timing adjustment by scanning the modulator timing domain with respective fine timing intervals (ΔT1R, ΔT2R) and respective relatively narrow modulator voltage signals (W1R, W2R), and again observing a change in detector counts for exchanged non-quantum signals. This operation is repeated until desired final modulator timings (T1F, T2F) and desired final activation signal widths (W1F, W2F) are obtained for the two modulators.

There is provided an image forming apparatus comprising: a scanning unit configured to scan, in accordance with image signals, a photosensitive member with laser light in a main scanning direction at a scanning speed that is not constant; an image signal generation unit configured to generate image signals that are changed such that the faster the scanning speed is, the narrower an image signal width becomes; a clock signal generation unit configured to generate sampling clock signals for sampling the image signals whose image signal width is changed such that the faster the scanning speed is, the shorter a sampling interval becomes; and a count unit configured to count image signals whose image signal width is changed based on the sampling clock signals.

Macroblock placement for an integrated circuit register-transfer level design is enhanced by tagging blocks having a set of functions as usage element definitions that have a minimum input signal width, such as tags added to a netlist of the design. Tagged blocks aid preferred and regular placement of library cells that are morphed to adapt for reduced congestion and improved utilization.

A method for decoding a DTMF tone which includes collecting the width of serial signals by measuring the time interval between zero-crossing points within a predetermined time; counting within the predetermined time the number of signal zero-crossing points; performing interpolation on the data produced by the collecting and counting steps with a Fourier transform; identifying a first frequency that has the strongest magnitude from the resulting data; and calculating the lower frequency of the tone being decoded by subtracting the first frequency from the average frequency of the digitized signal. The invention also includes apparatus that utilizes a zero-crossing detector for receiving a DTMF tone to be decoded and producing a digitized output; apparatus for collecting the width of serial signals by measuring the time interval between zero-crossing points within a predetermined time; apparatus for counting within the predetermined time the number of signal zero-crossing points; apparatus for performing interpolation on the data produced by the collecting and counting steps with a Fourier transform; apparatus for identifying a first frequency that has the strongest magnitude from the resulting data; and apparatus for calculating the lower frequency of the tone being decoded by subtracting the first frequency from the average frequency of the digitized signal.

The present invention discloses an accurate phase measurement method of a multipath multi-target echo signal. The concrete steps of the method are that a sending terminal emits a narrow pulse signal, the initial phases of the front and back adjacent pulses keep a certain difference value, and the design of a pulse width guarantees that the echo signal possesses a certain distance resolution ratio; a receiving terminal selects a segment of received signal at the specific position in each pulse by taking a synchronization pulse provided by the sending terminal as reference, and splices the multiple segments into a continuous wave signal of a long cycle; the continuous wave signal of the long cycle is carried out the narrowband filtering to filter the noise outside the band and improve the signal to noise ratio of a to-be-processed signal; the phase value of the filtered signal is calculated by utilizing Fourier transform. Compared with other signal processing method, the beneficial effects of the method are that: the continuous wave signal of the long cycle is spliced by an effective method, thereby facilitating the filtering of a noise component; the contradiction between the pulse width and the signal width can be solved effectively; the signal to noise ratio of a measurement signal and the phase measurement precision of the multi-target echo signal can be improved remarkably.

An ultrasonic measurement device 100 includes a pulse signal output circuit 110 that outputs a pulse signal having a rectangular wave based on a clock signal, and a resonance circuit 120 that is connected to an output node of the pulse signal output circuit 110, includes an ultrasonic transducer element, and has frequency characteristics of a low-pass filter. Also, the pulse signal output circuit 110 outputs a plurality of pulse signals that are different from each other in at least one of pulse signal voltage, pulse signal width, and pulse output timing.

The present invention provides a signal shaping method and device which relates to the digital signal processing technology. The signal shaping device is used to do regularized treatment to the input signal format, the device includes a burr filtration unit and a signal width adjustment unit, the input signal passes through the burr treatment unit and the signal width adjustment unit one by one and thereafter outputs to the later grade circuit, among which the burr filtration unit filters the input signals whose effective width are less than the burr width 'N' and keeps the input signals whose effective width are more than or equal to the burr width 'N' certain; the signal width adjustment unit adjusts the input signals to the signals with the regularized width 'M'. In addition, the invention also provides a signal shaping method. The signal shaping method and device of the invention can avoid all kinds of interferences to the circuit in actual environment and effectively simplify the design of the subsequent circuit by doing certain structuring to the input signal format.

We describe various embodiments of a level shift circuit and an associated method that achieve increased responsiveness by simultaneously adjusting the input signal width and shifting the voltage thereby reducing the number of logic gate stages needed for the two operations. A level shift circuit includes a delay unit for delaying an input signal via a plurality of stages to generate a plurality of delayed signals, and a signal width adjusting and level shifting unit for generating a first level of signal that is level-shifted in response to the input signal and a first delayed signal having the same phase as that of the input signal and generating a second level of signal in response to a second delayed signal having a different phase from that of the input signal.

The invention provides an offline processing method for metal film thickness data in a whole CMP (Chemical Mechanical Planarization) process. The offline processing method comprises the following steps: reading an output signal of an electric eddy sensor, and calculating a sampling signal according to the output signal; setting an amplitude threshold value of the sampling signal; traversing all sampling signals to obtain all non-zero point signal sections according to the amplitude threshold value; calculating the signal width of each non-zero point signal section, and determining a width threshold value of the sampling signals according to the signal width; traversing all non-zero signal sections in a measurement process again according to the amplitude threshold value and the width threshold value, extracting an effective measurement signal section, and calculating an average value of all data points in a central interval of each effective measurement signal section; acquiring the change information of metal film thickness in the whole CMP process according to the average value. According to the offline processing method, the influence of an interference signal and part abnormal signals in the measurement process can be effectively eliminated; a real copper layer thickness change can be calculated concisely and effectively; moreover, the calculation result accuracy is high.

The invention provides a single Hall sensor based calibration method for solar panel rotation accuracy. The method comprises the following steps: powering up a satellite, powering up a solar panel driving mechanism and a Hall sensor, and starting the solar panel driving mechanism to rotate; reading a preset width value of a Hall sensor signal from a ROM, setting the zero position of the solar panel, and calibrating the position of the solar panel at the time when the Hall sensor is triggered; starting an on-orbit solar tracking operation mode of the solar panel, automatically scanning signal width of the Hall sensor in each tracking period, and updating width value of the Hall sensor signal in the ROM; jumping to step 2 and performing execution circularly. Rotation errors of a solar paneldriving motor and sensor detection errors caused by magnetic steel magnetic weakening of the Hall sensor are eliminated, the on-orbit rotation accuracy of the solar panel is improved, and the method can be applied to rotation control tasks of satellite solar panels in various models.

The invention discloses a digital synthesis device for high-speed ultra-narrow pulses. After digital pulse signals pass through the digital synthesis device for the high-speed ultra-narrow pulses, controllable ultra-narrow pulse signals with the pulse width smaller than 200ps are generated. Due to the fact that the widths of the controllable ultra-narrow pulse signals depend on relative delay between falling edge signals and rising edge signals, synthesis of the ultra-narrow pulses with the adjustable pulse width can be achieved through control over a programmable delay line. Therefore, the whole digital synthesis device for the high-speed ultra-narrow pulses further improves digital synthesis capacity of the minimum pulse width, and has modularization performance of pulse width controllability.

The present invention relates to a pulse modulation method and the like having a structure for effectively suppressing nonlinear optical phenomena which increase as an optical pulse becomes wider when amplifying the optical pulse with a predetermined period as seed light. A modulator performs pulse modulation for a laser light source which is a seed light source or light outputted from the laser light source. A modulation pattern of a modulated voltage outputted from the modulator is adjusted such as to include a plurality of pulse components each having a signal width shorter than the pulse width of the optical pulse as an optical pulse generation pattern within a modulation period corresponding to a period of the optical pulse.

The present invention provides a frame synchronizer of T-DMB system receiver and its method, the device includes adder 1, selftimer 1, adder 2, selftimer 2. adder 3, a comparator, a sign counter and a decision control state machine, wherein the adders 1, 2, the selftimers 1, 2 are used for receiving input signal and the sending in the adder 3 after dot difference; the adder 3 sends the processing result to the comparator and then sends to the sign counter, the sign counter sends the enumerated data to the decision control state machine and receives the feedback of the decision control state machine. The frame synchronizer processes counting by receiving the signl of the signal width and the difference of threshold, and judging null interval, the method is quick and high effect, only using some control state machines and simple adding unit can realize because of having no filter, the method reduces the spending of the hardware, effectively overcomes time pulse.

The invention discloses a circuit structure for a counter and an electronic device applied to the circuit structure for the counter. The circuit structure for the counter and the electronic device are suitable for calculating the periodicity of one digital signal relative to one frequency signal, wherein the signal modal of the digital signal is a nonreturn-to-zero code. The circuit structure for the counter comprises a first counter module and a second counter module, wherein the first counter module receives the digital signal and the frequency signal; when the digital signal is in a high level, the first counter module calculates the periodicity of the signal width of the digital signal relative to the frequency signal; the second counter module receives an inverted signal of the digital signal and the frequency signal; and when the inverted signal of the digital signal is in a high level, the second counter module calculates the periodicity of the signal width of the inverted signal of the digital signal relative to the frequency signal. The counter circuit has a simplified structure, reduces the use amount of the components of a logic circuit, further reduces the occupied area of the circuit structure, lowers the power consumption, and facilitates the application of the integrated circuit.

The invention provides a superregenerative receiving device. An extinguishing controller of the device detects that the amplitude of the acquired oscillating signal reaches the preset amplitude and outputs control signals respectively to an oscillator and a delayer. The oscillator adjusts the non-oscillating time according to the frequency of the received external signal output by an antenna and the control signals output by the extinguishing controller and outputs the oscillating signal of the natural frequency. The delayer adjusts the width of the delay signal according to the control signals output by the extinguishing controller. A time width-amplitude converter converts the width of the delay signal output by the delayer into the sawtooth signal corresponding to the amplitude and outputs the sawtooth signal to a peak detector. The peak detector detects the peak of the amplitude of the received sawtooth signal and outputs the high / low level indicating the amplitude of the sawtoothwave to a shaping circuit. The shaping circuit shapes and filters the received signal and outputs the digital signal. The invention also provides a superregenerative receiving method. The device and the method can improve the data transmission speed.