51 results about "Process voltage temperature" patented technology

An SRAM employs a virtual rail configuration that is stable against process-voltage-temperature (PVT) variation. The SRAM provides a virtual power supply voltage to an SRAM cell that is obtained by lowering a power supply voltage by a threshold voltage of a transistor and a virtual ground voltage obtained by raising a ground voltage by a threshold voltage of a transistor. Due to the use of PMOS and NMOS transistors of diode types connected between the power supply voltage and the virtual power supply voltage and the use of NMOS and PMOS transistors of diode types connected between the ground voltage and the virtual ground voltage, a virtual power supply voltage level and a virtual ground voltage level that are stable even against various PVT variations are provided, so that low-leakage current characteristics are stable.

A voltage regulation subsystem for a microprocessor has both internal and external regulation modes. An internal auxiliary voltage regulator is selectively enabled to overdrive the voltage. The enablement of the auxiliary voltage regulator is contingent upon a comparison of bandgap references of the internal and external regulators used in the respective regulation modes, which boosts the supply voltage, enables circuitry supplied by the external regulator (with the assistance of auxiliary voltage regulators) to boot robustly in extreme Process-Voltage-Temperature (PVT) conditions.

A circuit for control of time for read operation is disclosed which additionally incorporates a dummy device circuit and a dummy sensitive amplifier circuit, uses a current mirror circuit to mirror a reference current in a reference device circuit into the dummy device circuit to generate a mirrored current, and generates time control signals based on the mirrored current. Due to the same adaptation of the mirrored current to the size of a test device as the reference current, the time control signals are also adapted to the size of the test device. This addresses the problem of fixed time control signals arising from the use of a conventional RC relay circuit and enables the time control signals to change with the size of the test device as well as Process Voltage Temperature, thereby resulting in an effective reduction in average energy consumed in read operation.

A design process optimization system and method for designing a circuit, which may be an integrated circuit (IC) employing adaptive voltage and scaling optimization (AVSO). In one embodiment, the system includes: (1) a process-voltage-temperature (PVT) libraries database configured to contain PVT libraries of PVT characterizations of devices of cells from which the circuit is to be constructed and (2) a PVT library selector coupled to the PVT libraries database and configured to receive a selection indicating a supplemental objective and respond to the selection by selecting one of the PVT libraries from the PVT libraries database, a timing signoff tool later employing at most two corners from the one of the PVT libraries to perform a timing signoff with respect to the circuit.

The invention provides a copy-on-write circuit suitable for a static random access memory. The copy-on-write circuit consists of a copy word line load, a copy bit line load, a copy bit line selector, a copy-on-write selector, a copy-on-write unit, a state machine, a line decoder, a storage array, a control circuit, a pre-decoder, a bit line selector, a sense amplifier and an input / output circuit, wherein the copy word line load is used for simulating load on a word line during normal write operation; the copy bit line load is used for simulating load on a bit line during the normal write operation; the copy bit line selector and the copy-on-write driver are used for simulating the bit line selector and the write driver during normal write operation; the copy-on-write unit is used for simulating a storage unit which is rewritten during the normal write operation; the state machine is used for switching between a start state and an end state for the normal write operation. By simulating normal '0' write operation, the accurate self-timing is provided for write operation under different process voltage temperatures of the static random access memory. Compared with the prior art, the copy-on-write circuit has the advantages that the bit line pulse width is reduced by 20 percent during the write operation.