1436 results about "Diode array" patented technology

A thin-film transistor includes a gate electrode having first and second gate electrode edges on opposed sides, and a drain electrode having a first edge that overlaps the first gate electrode edge, and a second edge that overlaps the second gate electrode edge. A diode array is fabricated by successive deposition of a conductive layer, a doped semiconductor layer and an undoped semiconductor layer adjacent to the substrate. A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line. Another display pixel unit provides reduced pixel electrode voltage shifts using a source line and a balance line.

In accordance with the invention, an illumination device comprises a substrate having a surface and a cavity in the surface. At least one light emitting diode (“LED”) is mounted within the cavity, and a monolayer comprising phosphor particles overlies the LED. The phosphor monolayer is adhered to the LED by a monolayer of transparent adhesive material. An optional optical thick layer of transparent material overlies the phosphor monolayer to encapsulate the LED and optionally to form a lens. Methods and apparatus for efficiently making the devices are disclosed.

The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages

A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types.

A surface-emitting laser diode device that oscillates in a direction perpendicular to the substrate is provided. This surface-emitting laser diode device includes: an active layer; a resonator structure including a first distributed Bragg reflector and a second distributed Bragg reflector that face each other and sandwich the active layer; a hole passage that extends from a first electrode to the active layer; an electron passage that extends from a second electrode to the active layer; a hole restricting structure that is located in the hole passage and defines a region for confining holes to the active layer; and an optical mode control structure that includes a non-oxide region provided in the resonator structure and an oxide region surrounding the non-oxide region, each region containing Al as a constituent element. In this surface-emitting laser diode, the area of the non-oxide region is smaller than the area of the hole restricting structure.

A thin-film transistor includes a gate electrode having a first gate electrode edge and a second gate electrode edge opposite the first gate electrode edge. The TFT also includes a drain electrode having a first drain electrode edge that overlaps the first gate electrode edge, and a second drain electrode edge that overlaps the second gate electrode edge. A method for fabricating a diode array for use in a display includes deposition of a conductive layer adjacent to a substrate, deposition of a doped semiconductor layer adjacent to the substrate, and deposition of an undoped semiconductor layer adjacent to the substrate. A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The unit includes a transistor, the pixel electrode, and the source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line. Another display pixel unit provides reduced pixel electrode voltage shifts. The unit includes a transistor, a pixel electrode, a source line and a balance line. The invention also provides a driver for driving a display provided with such a balance line.

A MOS or CMOS based photoconductor on active pixel image sensor. Thin layers of semi-conductor material, doped to PIN or NIP photoconducting layers, located above MOS and / or CMOS pixel circuits produce an array of layered photodiodes. Positive and negative charges produced in the layered photodiodes are collected and stored as electrical charges in the MOS and / or CMOS pixel circuits. The present invention also provides additional MOS or CMOS circuits for reading out the charges and for converting the charges into images. With the layered photodiode of each pixel fabricated as continuous layers of charge generating material on top of the MOS and / or CMOS pixel circuits, extremely small pixels are possible with almost 100 percent packing factors. MOS and CMOS fabrication techniques permit sensor fabrication at very low costs. In preferred embodiments all of the sensor circuits are incorporated on or in a single crystalline substrate along with the sensor pixel circuits. Techniques are disclosed for tailoring the spectral response of the sensor for particular applications.

A method for laser diode bar assembly. A method for assembling a modular stacked diode array is disclosed, whereby a diode bar is bonded between a pair of conductive spacers, as by soldering, to create a diode submodule. Each submodule, prior to being affixed to a substrate, may be individually pre-tested. Any number of diode bar submodules then may be affixed to a substrate to construct a diode bar array. A stacked array embodiment assembled according to the method provides for efficient cooling of the diode bars and electrical connection between diode bars while maximizing alignment of the diode bars. The spacers are connected to a conductive surface on a heat spreader. In the stacked array, one or more diode bars are alternated in series with two or more conductive spacers, with a series circuit provided from diode bar to diode bar. The spacers hold the diodes spaced apart from insulating grooves in the conductive layer on the substrate. Alternatively, thermally conductive separator fins extend from the heat spreader substrate to contact the diode bars situated between the spacers to promote rapid heat transfer from the diodes while maintaining the diode bars electrically isolated from tie conductive layer on the substrate.

A light-emitting diode array includes a substrate, an adhesive layer formed on the substrate, and a plurality of electrically connected epitaxial light-emitting stack layer disposed on the adhesive layer. Each of the epitaxial light-emitting stack layer has a P-contact and an N-contact coplanar to the P-contact. The light-emitting diode array has improved heat ventilation characteristics.

A light source (100) comprises a number of optical components aligned concentrically along an optical axis (115). The optical components include an array of light emitting diodes (101), a dielectric collimator (109) having surfaces configured to provide total internal reflection of light emitted from the array of diodes, and a second stage reflector (113) to further collimate the beam and which also may be based on total internal reflection by a prism structure on the outside.

High throughput liquid chromatography systems include multiple separation columns and multiple flow-through detection regions in sensory communication with a common radiation source and a multi-channel detector. Preferred detector types include a multi-anode photomultiplier tube, a charge-coupled device detector, a diode array, and a photodiode array. In certain embodiments, separation columns are microfluidic and integrated into a unitary microfluidic device. The optical path through a detection region is preferably coaxial with the path of eluate flow along a flow axis through a detection region. On-board or off-board detection regions may be provided.

A system and method for measuring an animal includes a light source and an optical source. The light source, which is preferably an array of monochromatic light emitting diodes, at least partially backlights one or more of the animal's legs. The optical sensor or device, which is preferably a single dimension camera or charged-coupled device, opposes the light source and obtains an image that includes silhouettes of one or more legs of the animal. A processor, such as a computer with software and data storage, determines measurements, such as the approximate skeletal trunk length of the animal, from the silhouetted legs in the image. One or more first ultrasound transducers can be arranged to determine an approximate height of the pelvic region, and one or more second ultrasound transducers can be arranged to determine an approximate width of the pelvic region.