The invention discloses a BCH (Bose,
Ray-Chaudhuri, Hocquenghem) decoding
system with pipeline structures, and belongs to the technical field of
computer memory error correction. The BCH decoding
system comprises a parallel correction factor computing module, a key equation solving-parallel
Chien search module, an FIFO (first in, first out)
memory module and a BCH decoding controller module. The parallel correction factor computing module is used for carrying out
parallel computing according to received data to obtain correction factors; the key equation solving-parallel
Chien search module isused for acquiring key equations by means of computing according to the correction factors and finding out solution of the key equations; the
FIFO memory module is used for aching data read from NAND(not and) Flash chips, and data in the
FIFO memory module can be outputted step by step when the solution of the key equations is computed; the BCH decoding controller module is used for implementingparallel execution on BCH decoding two-stage pipelines. The BCH decoding
system has the advantages that hardware resources in different modules in BCH decoders are reused, BCH decoding can be carriedout by the aid of the
parallel pipeline structures, accordingly, BCH
decoding throughput can be effectively improved, and the hardware expense can be reduced.