Multi-element LDPC code high-speed parallel decoder based on GPU, and decoding method thereof

Abstract

The invention discloses a multi-element LDPC code high-speed parallel decoder based on a GPU, and a decoding method thereof, and belongs to the technical field of the communication. The decoding method is divided into three stages: an initialization stage, a decoding stage and a judgment stage; once iterative decoding of the decoder is accomplished by only using a kernel function, the synchronization expenditure between the thread blocks and the starting expenditure of the kernel function are greatly reduced, and the access mount of the whole memory is lowered; the use rate of a hardware resource is maximized by designing different parallelism degrees under different systems, thereby improving the decoding throughput to 100M level. Through a memory-access way provided by the invention, theshared memory on a GPU chip is sufficiently utilized, the access to the whole memory is greatly reduced, and the memory-access efficiency and the memory-access bandwidth are improved.

Description

technical field [0001] The invention belongs to the technical field of communication, and relates to a high-speed decoder of multiple LDPC codes based on a Graphics Processing Unit (GPU, graphics processor). Background technique [0002] Davey and Mackay conducted research on the Sum Product Algorithm (SPA) of multivariate LDPC codes in 1998 (reference [1]: M.C.Davey and D.J.C.MacKay, "Low-density parity check codes over GF(q)," IEEE Communications Lett., vol.2, no.6, pp.165-167, 1998.). When the code length is medium and short codes, compared with binary LDPC, multivariate LDPC codes can obtain about 1dB coding gain, but this is at the cost of higher decoding complexity. On the premise of not losing decoding performance, in order to reduce the decoding complexity of multivariate LDPC codes, Mackay and Davey proposed an FFT-based SPA decoding algorithm in 2000, see reference [2]: D.J.C.MacKay and M.C.Davey, "Evaluation of Gallager codes for shortblock length and high rate ...

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Problems solved by technology

Such a design scheme will bring two major problems: 1) greatly increase the synchronization overhead between thread blocks and the startup overhead of kernel functions, and increase the access to global memory (the access bandwidth of global memory is limited); 2 ) When the number is small, the utilization rate of on-chip resources will drop seriously, and the performance of the GPU cannot be fully utilized

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