91results about How to "Reduce synchronization overhead" patented technology

The invention discloses a video decoding macro-block-grade parallel scheduling method for perceiving calculation complexity. The method comprises two critical technologies: the first one involves establishing a macro-block decoding complexity prediction linear model according to entropy decoding and macro-block information after reordering such as the number of non-zero coefficients, macro-block interframe predictive coding types, motion vectors and the like, performing complexity analysis on each module, and fully utilizing known macro-block information so as to improve the parallel efficiency; and the second one involves combining macro-block decoding complexity with calculation parallel under the condition that macro-block decoding dependence is satisfied, performing packet parallel execution on macro-blocks according to an ordering result, dynamically determining the packet size according to the calculation capability of a GPU, and dynamically determining the packet number according to the number of macro-blocks which are currently parallel so that the emission frequency of core functions is also controlled while full utilization of the GPU is guaranteed and high-efficiency parallel is realized. Besides, parallel cooperative operation of a CPU and the GPU is realized by use of a buffer area mode, resources are fully utilized, and idle waiting is reduced.

The invention relates to a redundant automation system (1), and a method for operating one such automation system (1). The inventive automation system comprises two automation appliances (3a, 3b) with which a common memory unit is associated, on which status data of the automation appliances (3a, 3b) can be stored. In this way, the automation appliances (3a, 3b) have direct access to a common database and a memory compensation is dispensed with in the event of an error during the switchover to the standby automation appliance (3b).

The invention discloses a data writing method and an apparatus for reducing synchronization overheads. The method comprises: acquiring data written from outside; copying the data to a log region for backup; determining cached pages corresponding to the data; in according with the cache mode of the cached page where the data are, making the data persistent. The method and apparatus of the invention, in accordance with frequency of data writing, adopt different cache modes, and merely store frequently written data to a Cache region, and reduces synchronization overheads written to an off-chip memory. And a scratch pad memory (SPM) which stores backup log to the chip without having to writing to the off-chip memory, which further reduces synchronization overheads.

The invention discloses a heterogeneous server structure-oriented graph calculation load balancing method. The method includes: calculating a variation coefficient of all processing times in a currentsuper step by a main control node according to the times used by processing graph calculation loads by all calculation nodes in the super step; if variation coefficients in two consecutive super steps are greater than a preset threshold value, determining that the graph calculation loads of all the calculation nodes in running are not balanced, and the graph calculation loads on the calculation nodes need to be re-assigned after the current super step ends; and otherwise, continuing to execute a next super step by all the calculation nodes. According to the method of the invention, vertex migration is utilized to balance processing times of the calculation nodes in each super step, thus synchronization overheads of all the calculation nodes in each super step are effectively reduced, a running time of a graph calculation task is shortened, and a resource utilization rate of each calculation node in running is increased.

The present invention discloses a method for multi-core instruction-set simulation. The proposed method identifies the shared data segment and the dependency relationship between the different cores and thus effectively reduces the number of sync points and lowers the synchronization overhead, allowing multi-core instruction-set simulation to be performed more rapidly while ensuring that the simulation results are accurate. In addition, the present invention also discloses a device for multi-core instruction-set simulation.

The invention discloses a distributed cache dynamic scaling method and system supporting load balancing, belonging to the technical field of software. The method is as follows: 1) each cache server regularly monitors its own resource utilization rate; 2) each cache server calculates its own weighted load value Li according to the currently monitored resource utilization rate, and sends it to the cache cluster manager; 3) cache The cluster manager calculates the current average load value of the distributed cache system according to the weighted load value Li. When it is higher than the threshold value thrmax, it performs an expansion operation; when it is lower than the set threshold value thremin, it performs a contraction operation. The system includes a cache server, a cache client and a cache cluster manager; the cache server is respectively connected to the cache client and the cache cluster manager through a network. The invention guarantees the balanced distribution of network traffic among each cache node, optimizes the utilization rate of system resources, and solves the problems of guaranteeing data consistency and continuous availability of services.

The invention relates to a carrier frequency synchronization method for a UFMC system based on an FPGA, and belongs to the field of wireless communication. According to the method, a UFMC symbol is used as a training sequence, and the training sequence contains the same symbols of m parts, wherein m is not less than 2; the whole frequency offset estimation process is completed through a decimal frequency offset and an integer frequency offset; and the decimal frequency offset is obtained through self-correlation of the two same data parts before and after the training sequence, and training sequence estimation after decimal frequency offset compensation is multiplied by a local training sequence and FFT is made to obtain the integer frequency offset. According to the method, the estimationprecision can be guaranteed through the decimal frequency offset estimation, and the system requirements can be met; through the integer frequency offset estimation, the overall estimation range is greatly increased. A system frequency offset value is effectively estimated, a bit error rate of the system is reduced, and the communication quality is improved.

The invention discloses a simultaneous frame and bit combined estimation method for an EBPSK (extended binary phase shift keying) communication system. The method comprises the steps: framing sending data at a transmitting end, and then performing EBPSK modulation; sending a receiving signal into an impact filter at a receiving end, and converting the receiving signal into parasitic amplitude modulation impact at a code element '1'; performing down sampling on output data of the impact filter according to a relative relation with a baseband code element rate; calculating peak values of 13 continuous data points of each group in a data stream subjected to down sampling, marking the moment that the peak values are greater than a certain threshold value, calculating a relevance value to a frame header, and marking the moment, in which four times of the peak value is smaller than the relevance value, in the marked moments; searching the first peak value of the relevance value in the marked moment in the step, wherein the moment corresponding to the first peak value is a synchronous moment. According to the simultaneous frame and bit combined estimation method, frame and bit are simultaneously finished by one step, so that the synchronization efficiency is improved, the synchronization precision is improved, the demodulation performance is high, the synchronization expense is reduced, the transmission efficiency is high, the hardware expenses are reduced, and the receiving machine implementation cost is reduced.

The present invention discloses a high-parallelism synchronization method for multi-core instruction-set simulation. The proposed method utilizes a new distributed scheduling mechanism for a parallel compiled MCISS. The proposed method can enhance the parallelism of the MCISS so that the computing power of a multi-core host machine can be effectively utilized. The distributed scheduling with the present invention's prediction method significantly shortens the waiting time which an ISS spends on synchronization.

The invention discloses a method for executing a dynamic allocation command on embedded heterogeneous multi-core in the technical field of computers. The method comprises the following steps of: partitioning a binary code program to obtain a plurality of basic blocks; respectively selecting each basic block so as to obtain a target processing core for executing each basic block; translating a basic block which corresponds to the obtained target processing core so as to obtain a translated binary code on the target processing core; and performing statistics on execution frequency of each basicblock, marking a basic block of which the execution frequency is greater than a threshold value T as a hot-spot basic block, and caching the translated binary code of the hot-spot basic block into the cache. The method dynamically allocates commands onto each heterogeneous multi-core to be executed according to the processing capacity and load condition of the system multi-core and the like, so that the method overcomes the defect that static scheduling cannot dynamically allocate resources and also reduces the complexity of dynamic thread division. Therefore, the execution efficiency of the program on the heterogeneous multi-core is further improved.

The invention relates to a data synchronization method and device and a related product, the product comprises a control module, and the control module comprises an instruction caching unit, an instruction processing unit and a storage queue unit; the instruction caching unit is used for storing a calculation instruction associated with the artificial neural network operation; the instruction processing unit is used for analyzing the calculation instruction to obtain a plurality of operation instructions; the storage queue unit is used for storing an instruction queue, and the instruction queue comprises a plurality of operation instructions or calculation instructions to be executed according to the front-back sequence of the queue. By means of the method, the operation efficiency of therelated product during operation of a neural network model can be improved.