BCH (Bose, Ray-Chaudhuri, Hocquenghem) decoding system with pipeline structures

Abstract

The invention discloses a BCH (Bose, Ray-Chaudhuri, Hocquenghem) decoding system with pipeline structures, and belongs to the technical field of computer memory error correction. The BCH decoding system comprises a parallel correction factor computing module, a key equation solving-parallel Chien search module, an FIFO (first in, first out) memory module and a BCH decoding controller module. The parallel correction factor computing module is used for carrying out parallel computing according to received data to obtain correction factors; the key equation solving-parallel Chien search module isused for acquiring key equations by means of computing according to the correction factors and finding out solution of the key equations; the FIFO memory module is used for aching data read from NAND(not and) Flash chips, and data in the FIFO memory module can be outputted step by step when the solution of the key equations is computed; the BCH decoding controller module is used for implementingparallel execution on BCH decoding two-stage pipelines. The BCH decoding system has the advantages that hardware resources in different modules in BCH decoders are reused, BCH decoding can be carriedout by the aid of the parallel pipeline structures, accordingly, BCH decoding throughput can be effectively improved, and the hardware expense can be reduced.

Description

technical field [0001] The invention belongs to the field of computer storage error correction, and more specifically relates to a BCH decoding system with a pipeline structure. Background technique [0002] With the wide application of non-volatile storage devices using NAND Flash as the medium, single-layer NAND Flash can no longer meet the requirements of large-capacity and low-cost storage. The new generation of multi-layer memory has low unit cost, high storage density, and large storage capacity. It is increasingly used in non-volatile storage systems. However, due to the increasingly smaller distance between the chip process and adjacent programming levels, the raw bit error rate (RBER) of NAND Flash has increased sharply. Traditional error-correcting codes have Unable to meet reliability requirements. As a cyclic code, BCH (Bose, Ray-Chaudhuri, Hocquenghem) code has excellent performance and simple structure, and is an error correction code technology widely used in...

AI Technical Summary

Problems solved by technology

However, the separate research on each module of the BCH decoder does not consider the circuit resource sharing in the BCH decoder as a whole, resulting in a large amount of hardware resource overhead

At present, a research team has proposed a syndrome-Qian search block circuit structure that shares hardware resources, which can reduce the overall hardware complexity of the BCH decoder, but it cannot implement the pipeline execution of the decoding process, which restricts the improvement of performance.

Images