37 results about "Charged-device model" patented technology

The invention provides a CDM (Charged Device Model) ESD (Electro-Static Discharge) protection circuit which is used for protecting a functional unit. The CDM ESD protection circuit comprises a first stage of ESD protection unit, a low voltage trigger protection unit, a second stage of ESD protection unit and a local ESD protection unit, wherein the first end of the low voltage trigger protection unit is coupled to the input/output pin, and the second end of the low voltage trigger protection unit is coupled to the substrate. When the electric potential of the substrate is smaller than that of the input/output pin and exceeds a second specific voltage, the low voltage trigger protection unit operates. Therefore, the performance of the CDM ESD protection circuit is improved.

A semiconductor integrated circuit is provided, which has an improved withstanding voltage for electrostatic breakdown at the time of electrostatic discharge by the charged device model, in the case of protecting a MOS capacitor provided at the input side of the internal circuit. The semiconductor integrated circuit comprises an internal circuit 20 for inputting an external signal, an internal circuit MOS capacitor 16, one end of which is connected to a power source wire 10 for supplying the source voltage and the other end of which is connected to a ground potential wire 12 for supplying the ground potential; a ground terminal 14 to which one end of the ground potential wire is connected; an electrostatic protection element 18 connected in parallel with the MOS capacitor 16 between the ground terminal 14 and the MOS capacitor, wherein the MOS capacitor and the electrostatic protection element are connected between the power source wire and the ground potential wire such that the wire resistance R1 of the ground potential wire between the ground terminal and the connection point with one end of the electrostatic protection element is larger than the wire resistance R2 of the ground potential wire between the connection point with one end of the electrostatic protection element and the connection point with one end of the MOS capacitor.

A semiconductor component having a tuned variable resistance resistor and a method for manufacturing the tuned variable resistance resistor. A semiconductor process for manufacturing a semiconductor component is selected. For the selected process, the tuned variable resistance resistor is characterized to determine the maximum stress current as a function of the width of the tuned variable resistance resistor. Then, for a given width and maximum stress current, the voltages across the resistors are characterized as a function of length. A tuned variable resistance resistor having a length and width capable of sustaining a predetermined maximum stress current is integrated into a semiconductor component. The semiconductor component may include protection circuitry designed in accordance with the Human Body Model, the Charge Device Model, or both.

The invention provides a CDM (Charged-Device-Model) electrostatic protection circuit. The CDM electrostatic protection circuit comprises an input and output pin, a power supply output terminal, a grounding terminal, a functional unit, a first level protection unit and a second level protection unit; the functional unit is connected with the input and output pin, the power supply output terminal and the grounding terminal; the first level protection unit is connected with the power supply output terminal and the grounding terminal; the second level protection unit is connected with the power supply output terminal and the grounding terminal; an inductance coil and a clamping circuit are connected in series between the first level protection unit and the second level protection unit; the clamping circuit is connected with the power supply output terminal and the grounding terminal. According to the CDM electrostatic protection circuit, the pulse voltage is mainly applied to two ends of the inductance coil when electrostatic pulses are produced and accordingly the voltage at two ends of each protection unit does not rapidly rise along with the electrostatic pulses and meanwhile the electrostatic pulses are released through the first level protection unit and the second level protection unit to implement the protection on the functional unit.

A Semiconductor integrated circuit with a protection circuit against electrostatic discharge. A clamping element is connected with MIS transistor to prevent the breakdown under the charged device model. A parasitic bipolar transistor, a MOS transistor or MIS transistor whose gate is composed of an insulating film thicker than that of the transfer gate, can be used as the clamping element.

An interface device coupled to a board on which integrated circuits are mounted for providing electrostatic discharge protection for the integrated circuits that comprises a plurality of first contact members, each of the first contact members including one end connected to the board and the other end to connect to an external device, and at least one second contact member connected to a voltage line of a voltage level, wherein the at least one second contact member includes a length greater than that of each of the first contact members.

The present invention provides a charged-device model (CDM) electrostatic discharge (ESD) protection circuit for an integrated circuit (IC). The ESD protection circuit comprises a substrate of first conductivity type; a MOS component of second conductivity type formed on a first well on the substrate, and coupled to a pad; an isolating well/region having the second conductivity type being formed between the first well and the substrate to separate the first well and the substrate. Additionally, the circuit comprises an ESD clamp coupled to the isolated well/region. Under normal power operation, the ESD clamp is open. During a CDM ESD event, the CDM charges accumulated in the substrate and the MOS component are removed by the ESD clamp to prevent damage to the IC.

A charged device model (CDM) electrostatic discharge (ESD) testing is carried out at wafer level. Wafer CDM pulses are repeatedly applied and monitored. The wafer CDM (WCDM) pulses are accomplished with a probe-mounted printed-circuit board and a high-frequency transformer that captures fast CDM pulses. Modeling of CDM and WCDM in the time and frequency domain illustrates the dominant effects, and shows that WCDM can reproduce all the major phenomena of package-level CDM testing.

The invention advances a CMOS process-based on-chip electrostatic discharge (ESD) protection circuit applied to radio frequency identification (RFID) chips, composed of chip ground on-chip ESD protection circuit used to connect two pressure points of an outside-chip antenna, and inside-chip circuit directly or indirectly connected with pressure points, and giving circuit structure and design method, where the on-chip ESD protection circuit for the RFID chip is an important solution to assure the chip avoids ESD failure. And it considers three discharging models of human body model (HBM), machine model (MM) and charging device model (CDM) and simultaneously considers validity of ESD protection circuit and insensibility to process, and it is an ESD protection circuit with strong robustness, applied to RFID chip.

The present invention relates to a semiconductor circuit, and more particularly, to a circuit for discharging static electricity, which is connected between an internal circuit and an input/output pad to provide a charge device model (CDM) discharging path. The circuit includes a plurality of input/output pads; a plurality of switching units corresponding one-to-one to the input/output pads and turned on in a low voltage state; resistors connected between the input/output pads and the switching units so as to correspond one-to-one to the input/output pads and the switching units; and a CDM discharge unit shared in serial by the plurality of the switching units and providing a ground path.

The present invention provides a CDM (Charged Device Model) current detection system and test method in an ESD (Electro-Static Discharge) electro-static protection. The objective of the invention is to complete the capture of the ESD current waveform of the CDM model so as to facilitate provide data support for ESD electro-static protection taking the CDM as a basis. The system structure comprises a testing machine configured for support, and the pedestal of the machine is provided with a test device DUT (DeviceUnder Test); a machine support is configured to fix the detection module of the system, and the detection module comprises a pogo (pogo stick) probe, a test plate and the like; the testing machine is made of aluminum alloy materials, has a lifting spiral regulation function and is provided with a fixing device capable of fixing the test plate of the device, and the test plate is a dual-layer FR-4 plate; and the pogo probe is a mobile phone antenna special probe capable of satisfying the signal test in the condition of the 18GHz and being less than 18GHz; and the characteristic impedance of a coaxial cable is 50 [Omega], the used calibration module (namely a calibration capacitor) is FR-4 materials, and a capacitance value is 4pF.

The invention relates to an antistatic test machine for a charging device model of an LQFP packaging chip, and relates to a semiconductor integrated circuit manufacturing technology, a plurality of LQFP packaging chip sockets are simultaneously arranged on a test board, and one LQFP packaging chip socket is arranged in a slot of each socket, so that the plurality of LQFP packaging chip sockets can be simultaneously carried on one test board; test time is saved in the antistatic test of the charging device model; and in addition, each LQFP packaging chip socket comprises a chip slot and a slot side wall which is formed by surrounding the slot, so that when the LQFP packaging chip is arranged in the chip slot, the pins of the chip extend out of the body of the chip and are borne on the first surface of the side wall of the slot to support the pins of the chip, and the pins of the chip are supported in the testing process, namely, the pins of the LQFP packaging chip are not suspended any more, so that accurate and lossless antistatic performance testing and subsequent functionality and parameter testing are ensured in the testing process, and the accuracy and the test efficiency of the chip-level test are improved.

The present invention discloses a CDM (Charged Device Model) protection circuit structure, and is suitable for the design of an ESD (Electro-Static Discharge) protection circuit. The CDM protection circuit structure is characterized in that: the CDM protection circuit structure can improve the CDM protection capacity of a radiofrequency signal input port in a radio frequency circuit, and mainly employs the ESD protection circuit performing dual-way low triggering for a power supply in a first-level ESD protection circuit and employs an ESD protection circuit performing dual-way low triggering for the ground at the same time. The CDM protection circuit structure employs the ESD protection circuit performing dual-way low triggering for the power supply and employs the ESD protection circuit performing dual-way low triggering at the same time in a second-level ESD protection circuit, and in the CDM event, when the radio-frequency signal input port is earthed, the circuit can effectively release the electrostatic charge in the substrate and play the CDM protection effect.

A current sensor for use with a charged device model (CDM) tester includes an outer conductor and a cylindrical inner conductor. The inner conductor is positioned within a central cylindrical bore of the outer conductor to provide a characteristic transmission line impedance of approximately 50 ohms. A test probe conductor extends from the distal end of the inner conductor and is electrically connected to the inner conductor. An array of self-supporting ceramic chip resistors is radially positioned between the distal ends of the inner conductor and the outer conductor to provide a uniformly distributed resistance between the inner conductor and the outer conductor. When the test probe conductor is applied to a pin of a charged device under test (DUT), a discharge current passes through the resistors and produces a voltage on the inner conductor that is provided as a signal voltage proportional to the discharge current.