38results about How to "Threshold Voltage Adjustment" patented technology

The invention discloses a thin-film transistor, a manufacture method of the thin-film transistor, an array substrate and a display device, belongs to the field of electrical elements, and aims to solve the problems of over etching of gate insulating layers and instability of electrical properties in the prior art. The thin-film transistor comprises a substrate, a gate, a first gate insulating layer and an active layer. The gate, the first gate insulating layer and the active layer sequentially disposed on the substrate. The gate is wrapped by the first gate insulating layer. The first gate insulating layer is wrapped by the active layer. The first gate insulating layer is made of alumina and other materials.

The invention provides a semiconductor device and a preparation method thereof, relating to the technical field of semiconductors. The preparation method of the semiconductor device has the beneficial effect that regulation of threshold voltages of transistors is achieved by adding cap layers and barrier layers in a gate laminated structure, so that the semiconductor device with multiple threshold voltages can be better achieved. Regulation of the threshold voltages of the transistors can be achieved as the cap layers and the barrier layers are added in the gate laminated structure, so that the semiconductor device has better threshold voltage characteristics.

The invention discloses a semiconductor integrated circuit with HKMG, comprising: a semiconductor device is formed on an FDSOI substrate structure, the work function of the work function layer of HKMG tends to the middle value of the forbidden band width of the top semiconductor layer; the FDSOI substrate The bottom structure has an adjustment structure of the threshold voltage of the semiconductor device. The adjustment structure of the threshold voltage of the semiconductor device includes an inversion channel doping structure and a substrate bias application structure. The threshold voltage of the semiconductor device is adjusted by the threshold voltage adjustment structure of the semiconductor device, the influence of the work function layer on the threshold voltage of the semiconductor device is offset, and a semiconductor device with a threshold voltage meeting requirements is formed. The invention can unify the structure of the HKMG of the PMOS transistor and the NMOS transistor, and can eliminate the metal grid boundary effect produced when the HKMG of the PMOS transistor and the NMOS transistor are different.

A method for forming a semiconductor structure, comprising: providing a substrate; forming a work function layer on the substrate, the step of forming the work function layer includes one or more steps of forming a work function film, and the step of forming the work function film includes: An initial work function film is formed on the substrate, and the initial work function film has carbon atoms; the carbon removal precursor is used to remove carbon from the initial work function film to form a work function film, and the carbon removal precursor is used to interact with The carbon atoms in the initial work function film react; a gate is formed on the work function layer. A gate is formed on the work function layer. After the initial work function film is formed, the carbon removal treatment is performed on the initial work function film through the carbon removal precursor. The carbon-removing precursor can react with the carbon atoms in the initial work function film, thereby reducing the carbon atom content in the initial work function film, thereby changing the work function of the work function layer, and then adjusting the threshold voltage of the formed transistor, so that all The threshold voltage of the formed transistor meets the design requirements.

The invention discloses a threshold voltage adjusting method which is applied to a manufacturing process of a deep N-well high-voltage CMOS integrated circuit and can be used for adjusting threshold voltage of a high-voltage CMOS on the premise that a photoetching layer is not increased. The method includes the steps that when a first P well, a second P well and a third P well of the deep N-well high-voltage CMOS integrated circuit are formed, first ions according with first preset conditions are injected into the first P well, the second P well and the third P well, the first ions are injected in twice, and accordingly source drain breakdown voltage and threshold voltage of a high-voltage NMOS and source drain breakdown voltage and threshold voltage of a high-voltage PMOS are adjusted.

The invention discloses a method based on micron-scale technique for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid. The process includes the following steps: fabricating an N / P well and growing a Poly- SiGe / SiN / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiO2; etching away the SiO2layer on the surface of the substrate, except the SiO2 at the side wall of Poly-Si; based on the etching ratio of Poly-Si to SiN(11:1), etching the Poly-Si on the surface of SiN; based on the ratio of SiN to SiO2(2:1), etching the SiN, except the SiN in the protective area on the side wall of SiO2; based on the etching ratio of Poly-SiGe to SiO2(50:1), etching the Poly-SiGe, except the Poly-SiGein the protective area on the side wall of SiO2 so as to form an n / p MOSFET grid; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form ann / p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 45-90nm. The method can fabricate a CMOS integrated circuitwhich has a polycrystal SiGe grid on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

The invention discloses a method for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid through SiN masking technique. The process includes the following steps: fabricating an N / P well and growing a Poly- SiGe / SiN / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiN; etching the SiN layer onthe surface, except the SiN at the side face of the window; based on the etching ratio of Poly-Si to SiN (11:1), etching the Poly-Si at the surface of SiN and etching the SiN except on the side wallof SiN so as to expose the substrate of Poly-SiGe; based on the etching ratio of Poly-SiGe to SiN(11:1), etching the Poly-SiGe except on the side wall of the SiN so as to form an n / p MOSFET grid; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so as to forma CMOS integrated circuit with a conducting channel at 45-90nanometer. The method can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

The invention discloses a trench gate power device manufacturing method, and the method comprises the steps: forming a hard mask layer, carrying out the photoetching and forming a trench; carrying out the self-aligning channel injection with an inclination angle; continuing the etching of a semiconductor substrate at the bottom of a trench, so as to remove the channel injection impurities on the surface of the bottom of the trench; forming a gate medium layer and a polysilicon gate; adding an opening of the hard mask layer, and carrying out the self-aligning source injection; removing the hard mask layer; carrying out the complete body region injection; forming a contact injection layer with the depth being less than the depth of a source region, and forming an interlayer film and a contact hole; carrying out the self-aligning contact injection formation after the contact injection layer is formed through complete contact injection before the interlayer film is formed or after the etching of the contact hole; placing metal in the contact hole, and forming ohmic contact with the contact injection layer. The invention also discloses a trench gate power device. The method can prevent the contact hole from passing through a source region, can improve the stability of a threshold voltage of the device, can reduce the size of a device unit, and can reduce the conduction resistance.

An isolation structure of a semiconductor device, a manufacturing method thereof and a semiconductor device including the same are provided. The isolation structure (209) comprises: a trench buried in a semiconductor substrate (200); an oxide layer (207) covering the bottom and the side walls of the trench; and isolation materials (210) positioned on the oxide layer in the trench; wherein, lanthanum enriched oxides (206) is included in the oxide layer on the upper portions of the side walls of the trench. By using the trench isolation structure, the metal lanthanum in the lanthanum enriched oxide may diffuse into the corner of the oxide layer of the gate stack (300), therefore, influence introduced by short-channel effects can be lowered, and meanwhile, threshold voltage can be adjusted.

The invention discloses a method for manufacturing a semiconductor device. The method includes the following steps of: providing a semiconductor substrate; forming a first semiconductor layer on the substrate, and forming a second semiconductor layer on the substrate and the first semiconductor layer, wherein first isolations are formed on the substrate, and the second semiconductor layer on the first semiconductor layer is an active area for forming a device structure; forming through etching holes in the second semiconductor layer on the first semiconductor layer; etching and removing the first semiconductor layer through the etching holes to form a cavity; forming a dielectric layer on the inner surfaces of the cavity and the etching holes, and adding conductor layers into the cavity and the etching holes to respectively form a back gate and connection holes; and forming second isolations of the device structure on the substrate at two side of the gate and between the first isolations and the back gate. According to the method, an SOI device can be obtained through the substrate; and through the dielectric layer formed on the cavity and the etching holes and the back gate formed by adding the conductor layers, the threshold voltage of the device can be adjusted, and the process is simple and is easy to operate.

The invention discloses a novel GaN-based enhanced HEMT device. The novel GaN-based enhanced HEMT device comprises a GaN intrinsic layer, a barrier layer, a high-hole-concentration structural layer, a first metal electrode, a second meta electrode, a third metal electrode, a passivating dielectric layer and a passivating protection layer, wherein the GaN intrinsic layer and the barrier layer sequentially grow on a substrate, the high-hole-concentration structural layer covers the partial area of the upper surface of the barrier layer, the first metal electrode and the second meta electrode are located in the partial area which is not covered by the high-hole-concentration structural layer, of the upper surface of the barrel layer, the third metal electrode covers the upper surface of the high-hole-concentration structural layer, the passivating dielectric layer covers the upper surface of the obtained substrate and forms a table top graph, and the passivating protection layer covers the upper surface of the passivating dielectric layer. The invention further discloses a manufacturing method of the novel GaN-based enhanced HEMT device. The novel GaN-based enhanced HEMT device is high in reliability and good in repeatability, adjustment of device threshold voltage can be achieved by selecting different component gradual change ranges, different nitride alloys and the dosage concentration and thickness of the different nitride alloys, and the manufactured device can meet different requirements.

A structure and manufacturing method of a semiconductor device, comprising: providing a semiconductor substrate; forming a first semiconductor layer on part of the substrate, forming a second semiconductor layer on the substrate and the first semiconductor layer, and forming isolation on the substrate, wherein , the first semiconductor layer includes a first part located in part of the active region and a second part extending toward the end of the gate, the first part is as wide as the active region in the gate width direction and has a width greater than or equal to the gate length direction Long; form a device structure on the active region of the second semiconductor layer, the gate of the device structure is located above the first part; form a through etching hole in the second semiconductor layer above the second part; through the etching hole Etching and removing the first semiconductor layer to form a cavity; forming a dielectric layer on the inner surface of the cavity and the etching hole, and filling the cavity and the etching hole with the conductor layer. The invention can form the back gate structure by filling the dielectric layer and the conductor layer in the cavity and the etching hole, realize the adjustment of the threshold voltage of the device, and the process is simple and easy.

The invention discloses a method based on SiO2 masking technique for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid. The process includes the following steps: fabricating an N / P well and growing a Poly- SiGe / SiO2 / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiO2; etching the SiO2 layer on the surface, except the SiO2 at the side face of the window; based on the etching ratio of Poly-Si to SiO2 (50:1), etching the Poly-Si at the upper layer; based on the etching ratio of Poly-SiGeto SiO2 (50:1), etching the SiO2 and the Poly-SiGe, except the SiO2 and Poly-SiGe in the protective area at the side wall of the SiO2, preserving the SiO2 and Poly-SiGe below the side wall, forming an / p MOSFET grid and depositing a layer of SiO2; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 65-90nm. The method can fabricate a CMOS integrated circuit which is improved in performanceby 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.