Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method for preparing polycrystal SiGe gate nano CMOS integrated circuit by micro process

An integrated circuit, micron-level technology, applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., can solve the problems of increasing the difficulty of process manufacturing and limited adjustment range of device threshold voltage, so as to improve manufacturing capacity and reduce process difficulty , The effect of increasing the degree of integration

Inactive Publication Date: 2009-02-04
XIDIAN UNIV
View PDF0 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method has a limited range of adjustment to the threshold voltage of the device, and also increases the difficulty of process manufacturing, making it a process bottleneck.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for preparing polycrystal SiGe gate nano CMOS integrated circuit by micro process
  • Method for preparing polycrystal SiGe gate nano CMOS integrated circuit by micro process
  • Method for preparing polycrystal SiGe gate nano CMOS integrated circuit by micro process

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0032] Embodiment 1: the CMOS integrated circuit with the polycrystalline SiGe grid of 45nm is prepared on the Si substrate that conduction channel is, concrete steps are as follows:

[0033] Step 1, depositing a masking layer, as shown in Figure 2(a).

[0034] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 Left and right p-type Si substrate sheets 1;

[0035] (1b) Thermally oxidize a layer of SiO with a thickness of 20 nm on the substrate 2 buffer layer 2;

[0036] (1c) on SiO 2A SiN layer 3 with a thickness of 110nm is deposited on the buffer layer by means of low pressure chemical vapor deposition LPCVD, which is used for the masking of well implantation.

[0037] Step 2, forming a well region, as shown in FIG. 2(b).

[0038] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0039] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is ther...

Embodiment 2

[0068] Embodiment 2: on the SOI substrate, the CMOS integrated circuit with the polycrystalline SiGe gate with a 65nm conductive channel is prepared, and the specific steps are as follows:

[0069] Step 1, depositing a masking layer, as shown in Figure 2(a).

[0070] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 left and right p-type SOI substrates 1;

[0071] (1b) Thermally oxidize a layer of SiO with a thickness of 30 nm on the substrate 2 buffer layer 2;

[0072] (1c) on SiO 2 A 120nm-thick SiN layer 3 is deposited on the buffer layer by means of APCVD for the masking of the implantation in the well region.

[0073] Step 2, forming a well region, as shown in FIG. 2(b).

[0074] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0075] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized on the surface of the P well regi...

Embodiment 3

[0104] Embodiment 3: the CMOS integrated circuit with the polycrystalline SiGe gate that the conductive channel is 90nm is prepared on the Si substrate, the specific steps are as follows:

[0105] Step 1, depositing a masking layer, as shown in Figure 2(a).

[0106] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 Left and right p-type Si substrate sheets 1;

[0107] (1b) Thermally oxidize a layer of SiO with a thickness of 40 nm on the substrate 2 buffer layer 2;

[0108] (1c) on SiO 2 A 140nm-thick SiN layer 3 is deposited on the buffer layer by plasma-enhanced chemical vapor deposition (PECVD) for the masking of well implantation.

[0109] Step 2, forming a well region, as shown in FIG. 2(b).

[0110] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0111] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized on the surfa...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a method based on micron-scale technique for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid. The process includes the following steps: fabricating an N / P well and growing a Poly- SiGe / SiN / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiO2; etching away the SiO2 layer on the surface of the substrate, except the SiO2 at the side wall of Poly-Si; based on the etching ratio of Poly-Si to SiN(11:1), etching the Poly-Si on the surface of SiN; based on the ratio of SiN to SiO2(2:1), etching the SiN, except the SiN in the protective area on the side wall of SiO2; based on the etching ratio of Poly-SiGe to SiO2(50:1), etching the Poly-SiGe, except the Poly-SiGe in the protective area on the side wall of SiO2 so as to form an n / p MOSFET grid; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 45-90nm. The method can fabricate a CMOS integrated circuit which has a polycrystal SiGe grid on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a method for manufacturing nanoscale Si integrated circuits by using the existing micron-scale Si integrated circuit manufacturing process. Background technique [0002] Electronic information technology is the core technology of the national economy. It serves all fields of the national economy. Microelectronics technology is the key to electronic information technology, and integrated circuits are the key among the keys. Since the advent of integrated circuits in 1958, they have developed at an astonishing speed. They have become the core of information science and technology, the cornerstone of national economic development and national defense construction, and have had a huge impact on world politics, economy and culture. As the fastest-growing, most influential, and most widely used technology in human history, integrated circuits have ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/8238
Inventor 胡辉勇张鹤鸣舒斌宣荣喜戴显英宋建军赵丽霞屈江涛徐小波
Owner XIDIAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com