40results about How to "Reduce soft error rate" patented technology

A silicon and silicon germanium based semiconductor MODFET device design and method of manufacture. The MODFET design includes a high-mobility layer structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave, sub-millimeter-wave and millimeter-wave. The epitaxial field effect transistor layer structure includes critical (vertical and lateral) device scaling and layer structure design for a high mobility strained n-channel and p-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate capable of achieving greatly improved RF performance.

A butted contact structure forming a source contact electrically connecting a voltage node and a well region and method for forming the same, the butted contact structure including an active region having a well region disposed adjacent an electrical isolation region on a semiconductor substrate; a MOSFET device including a source and drain region on the active region; and, a conductive contact having a first portion formed to the source region and a second portion formed through the electrical isolation region to the doped well region.

An electronic component is disclosed, having a plurality of microelectronic spring contacts mounted to a planar face of the component. Each of the microelectronic spring contacts has a contoured beam, which may be formed of an integral layer of resilient material deposited over a contoured sacrificial substrate, and comprises a base mounted to the planar face of the component, a beam connected to the base at a first end of the beam, and a tip positioned at a free end of the beam opposite to the base. The beam has an unsupported span between its free end and its base. The microelectronic spring contacts are advantageously formed by depositing a resilient material over a molded, sacrificial substrate. The spring contacts may be provided with various innovative contoured shapes. In various embodiments of the invention, the electronic component comprises a semiconductor die, a semiconductor wafer, a LGA socket, an interposer, or a test head assembly.

A semiconductor device is composed of a first circuit receiving a first power supply voltage; and a second circuit receiving a second power supply voltage. The second power supply voltage is higher than the first power supply voltage. Such device arrangement is effective for reducing the soft error rate, when the second circuit is more susceptive to a soft error than the first circuit, especially when the second circuit is a memory device.

Approaches for adjusting the recording density of a recording medium in a circumferential direction are disclosed. A hard-disk drive includes one or more electronic components configured to divide a track, of a plurality of concentric tracks on a magnetic-recording disk, into a plurality of portions, and write data to each of the plurality of portions at a recording density that is independent of the recording density used for any of the other portions. Data may be written to a first portion of a track at a different frequency than to a second portion of the same track. The frequency at which data is written may be adjusted for different portions of the same track to allow the frequency to be reduced at certain portions shown to have relatively higher soft error rate while increasing the frequency for other portions to achieve a desired average error rate for the track.

Disclosed is a SRAM cell and a method of manufacturing the same. The SRAM cell comprises: a pair of access devices; a pair of pull-up devices; a pair of pull-down devices; and at least one metal plate formed on metal interconnection lines in contact with a substrate, having a dielectric film interposed between the metal plate and the metal interconnection lines, so as to increase a cell capacitance, thereby reducing a soft error rate. Herein, one metal plate may be included in each cell. In this case, the metal plate overlaps with a first one of metal interconnection lines of a node side and a node bar side, while being in contact with a second one of the metal interconnection lines of the node side and the node bar side. Also, two metal plates may be included in each cell. In this case, the metal plates overlap, respectively, with one metal interconnection line of metal interconnection lines of a node side and a node bar side, while being in contact with another metal interconnection line of the node side or the node bar side, respectively. Therefore, capacitance is additionally formed to increase cell capacitance, so that variation of the electric potentials of cell nodes, which is caused by generated electrons, is prevented, and thereby soft error can be efficiently reduced.

A latch circuit includes: first nodes which are three or more and to which a voltage in a first signal level is set; second nodes which are three or more and to which a voltage in a second signal level obtained by inverting the first signal level is set; and first node voltage control circuits having the first nodes; and second node voltage control circuits having the second nodes. Each of the first node voltage control circuits is connected with at least two of the three or more second nodes, and controls the voltage of the first node based on the voltages of the at least two second modes. Each of the second node voltage control circuits is connected with at least two of the three or more first nodes and controls the voltage of the second node based on the voltages of the at least two first nodes.

An integrated circuit semiconductor memory device having the BOX layer removed from under the gate of a storage transistor to increase the gate-to-substrate capacitance and reduce the soft error rate. The increased node capacitance thus obtained is achieved without requiring a corresponding increase in area.

A current-assisted magnetic recording write head has an electrically conductive layer in the write gap between the write pole and the trailing shield. Electrical circuitry directs current between the write pole and the trailing shield, through the conductive layer in the write gap. The current through the conductive layer generates an Ampere field substantially orthogonal to the magnetization in the write pole to assist magnetization switching of the write pole. The conductive layer is wider in the cross-track direction than the trailing edge of the write pole and may extend beyond the write pole side gaps so as to be in contact with both the side shields and the trailing shield. The conductive layer may have substantially the same along-the-track thickness across its width or it may have a thicker central region at the write pole trailing edge and thinner side regions.

The invention discloses a fault-tolerant directory cache controller for the problem that a conventional directory cache is poor in fault tolerance and low in reliability, and cannot meet the requirements of a spatial environment or a complicated electromagnetic environment. The fault-tolerant directory cache controller comprises four identical directory cache bodies, a directory access bypass, a directory access crossbar switch, an access crossbar switch and a configuration register. By designing the four directory cache bodies, the configuration register, the full interconnected access crossbar switch and the directory access crossbar switch, two working modes can be flexibly configured, so that both the performance and the fault tolerance are preferred. By designing a directory access bypass module, the complete failure of a directory Cache function in a bad condition such as a space high-radiation environment is prevented, so that the reliability is enhanced. Compared with the conventional directory Cache, the fault-tolerant directory cache controller has the advantages that a multilevel fault-tolerant technology from a system structure level to a circuit design level is adopted, so that on the premise of no performance loss, the fault tolerance and reliability of the directory Cache are remarkably improved.

A semiconductor device and a method for forming the same, wherein the method for forming the semiconductor device includes: providing a substrate, the substrate including a first semiconductor layer, an insulating layer positioned on the surface of the first semiconductor layer, and a second semiconductor layer positioned on the surface of the insulating layer, The substrate has a first region, a second region and a third region, the second region is adjacent to the first region and the third region, wherein the thickness of the insulating layer in the first region and the third region is greater than that of the insulating layer in the second region The bottom surface of the insulating layer in the first region, the second region and the third region is flush; the gate structure is formed on the surface of the second semiconductor layer in the second region; the first region and the third region on both sides of the gate structure A doped region is formed in the second semiconductor layer. The thickness of the insulating layer under the gate structure of the present invention is smaller than the thickness of the insulating layer under the doped region. Since the effective resistance of the insulating layer under the gate structure is small, the threshold voltage of the semiconductor device can be effectively improved.

The invention discloses a static random access memory (SRAM) half-select disturb elimination structure based on a hierarchical bit line structure. The SRAM half-select disturb elimination structure based on the hierarchical bit line structure comprises a storage array which has the hierarchical bit line structure; each storage unit of the storage array has a single reading operation branch; each column of the storage array is divided into a plurality of sub-modules. According to the SRAM half-select disturb elimination structure based on the hierarchical bit line structure, by utilizing virtual ground wire control, a ground wire of the reading operation branch of each storage unit in each sub-module is singly guided out, and is uniformly connected with an actual ground wire through a ground wire control switch; additionally, column selection signals Col of a corresponding column of each sub-module control a conduction state of each ground wire control switch, and a bit line discharge path of an unselected column unit during a reading operation is switched off, so that static power consumption caused by half select disturb is completely eliminated; however, due to utilization of a local bit line suspension technology, unselected column is forced to locally suspend in a writing operation, so that a short circuit discharge path is eliminated; meanwhile, the disturbance of local bit lines to a half-select unit is effectively reduced, so that unit robustness is improved, and noise margin is increased.