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Fault-tolerant directory cache controller

A directory cache and controller technology, applied in memory systems, instruments, electrical digital data processing, etc., can solve problems such as poor fault tolerance, low reliability, and inability to meet the space environment or complex electromagnetic environment of the directory cache

Active Publication Date: 2016-07-06
NAT UNIV OF DEFENSE TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0026] The main technical problem to be solved by the present invention is: Aiming at the traditional directory Cache having weak fault tolerance and low reliability, and unable to meet the requirements of the space environment or complex electromagnetic environment, a fault-tolerant directory Cache controller is proposed, which adopts the system structure level to the circuit The design-level multi-level fault-tolerant technology significantly improves the fault-tolerance and reliability of the directory cache without loss of performance

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Embodiment Construction

[0095] Embodiments of the present invention will be described below through specific examples.

[0096] Such as Figure 4 As shown, the fault-tolerant directory Cache controller of the present invention consists of 4 identical DCB modules, 1 directory access bypass DAP module, 1 directory access crossbar DAX module, 1 memory access crossbar MAX module and 1 configuration register constitute. The four directory cache bodies are respectively recorded as the zeroth directory cache body DCB 0 , the first directory cache body DCB 1 , the second directory cache body DCB 2 and third directory cache body DCB 3 , the internal structure and connection relationship of the four directory cache bodies are exactly the same. The connection relationship between each component is: the directory access cross switch DAX is connected to the external interface through the request message signal and the read return message signal, and the DCB 0 、DCB 1 、DCB 2 、DCB 3 , DAP is co...

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Abstract

The invention discloses a fault-tolerant directory cache controller for the problem that a conventional directory cache is poor in fault tolerance and low in reliability, and cannot meet the requirements of a spatial environment or a complicated electromagnetic environment. The fault-tolerant directory cache controller comprises four identical directory cache bodies, a directory access bypass, a directory access crossbar switch, an access crossbar switch and a configuration register. By designing the four directory cache bodies, the configuration register, the full interconnected access crossbar switch and the directory access crossbar switch, two working modes can be flexibly configured, so that both the performance and the fault tolerance are preferred. By designing a directory access bypass module, the complete failure of a directory Cache function in a bad condition such as a space high-radiation environment is prevented, so that the reliability is enhanced. Compared with the conventional directory Cache, the fault-tolerant directory cache controller has the advantages that a multilevel fault-tolerant technology from a system structure level to a circuit design level is adopted, so that on the premise of no performance loss, the fault tolerance and reliability of the directory Cache are remarkably improved.

Description

technical field [0001] The invention relates to an on-chip multi-core microprocessor and a fault-tolerant directory cache (Cache) controller in a node control chip. Background technique [0002] In recent years, from supercomputers to personal computers, from consumer electronics to industrial control, all aspects of human production and life have been inseparable from Very Large Scale Integrated (VLSI) chips. In digital integrated circuits, logic "1" or logic "0" is expressed by holding or releasing a certain charge. Integrated circuits used in complex electromagnetic environments (such as space and nuclear power plants) are bombarded by high-energy particles or disturbed by noise, which will cause instantaneous charge and discharge, which may damage the internal state of the microprocessor and affect the reliability of the chip. Such errors, caused by high-energy particle bombardment and noise interference, are called "soft errors." Compared with the "hard errors" introd...

Claims

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Application Information

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IPC IPC(8): G06F12/0817G06F12/0888
CPCG06F12/0817G06F12/0888
Inventor 张建民黎铁军肖立权庞征斌王克非常俊胜齐星云徐金波罗章董德尊赖明澈黎渊徐实马柯帆
Owner NAT UNIV OF DEFENSE TECH
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