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Latch circuit and flip-flop circuit

A technology of latch circuit and trigger circuit, which is applied in the direction of electrical components, electric pulse generation, pulse generation, etc., can solve the problems that soft errors cannot be suppressed, can not suppress soft errors, etc., and achieve the goal of suppressing soft errors and reducing the soft error rate Effect

Inactive Publication Date: 2009-05-13
NEC ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] In recent years, a charge-sharing problem has been pointed out: the collection of charge generated by a radiation incident by two or more nodes
[0011] Similar to the technique described in prior art 1, there are cases where soft errors cannot be suppressed depending on the location of charge collection when charge collection has occurred in multiple nodes
[0012] As mentioned above, in conventional technology, when charges are collected by multiple memory nodes through charge sharing, it is impossible to suppress soft errors

Method used

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  • Latch circuit and flip-flop circuit
  • Latch circuit and flip-flop circuit
  • Latch circuit and flip-flop circuit

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0030] FIG. 4 is a circuit diagram showing the configuration of the latch circuit 10 according to the first embodiment of the present invention. The latch circuit 10 in the first embodiment is provided with: three or more nodes N1A, N1C, N1E, and N1G as the first node in which the voltage of the first signal level is set; Three or more nodes N2B, N2D, N2F, and N2H in which the voltage of the second signal level obtained by inverting the first signal level is set. For example, when data "1" is set in nodes N1A, N1C, N1E, and N1G, data "0" obtained by inverting the data "1" is set in nodes N2B, N2D, N2F, and N2H. Here, transmission gates (not shown) are connected to nodes N1A, N1C, N1E, and N1G as first nodes, and receive data latched by the latch circuit through the nodes N1A, N1C, N1E, and N1G. In addition, transmission gates may be connected between the nodes N1A, N1C, N1E, and N1G as the first node and the nodes N2B, N2D, N2F, and N2H as the second node. Hereinafter, the p...

no. 2 example

[0069] The latch circuit 10 shown in FIG. 4 may be changed within a part of its configuration. For example, any one of the P-channel type MOS transistor MP1A to the N-channel type MOS transistor MN2H for suppressing the voltage value of the data holding node may be eliminated from the latch circuit 10 shown in FIG. 4 . FIG. 6 is a circuit diagram showing a latch circuit 10 according to a second embodiment of the present invention. In the latch circuit 10 shown in FIG. 6, the P-channel type MOS transistors MP2B, MP2D, MP2F, and MP2H and the N-channel type MOS transistor MN2B are removed from the configuration of the latch circuit 10 shown in FIG. , MN2D, MN2F, and MN2H.

[0070] Since transistors having less influence of noise signals are removed in the latch circuit 10 shown in FIG. 6, although the latch circuit 10 has a higher soft error generation rate than the circuit shown in FIG. It also has the effect of reducing the circuit area. It is effective to use the circuit sh...

no. 3 example

[0072] Furthermore, any one of the node voltage control circuits 1A to 1H can be reduced from the flip-flop circuit 10 shown in FIG. 4 . FIG. 7 is a circuit diagram showing the configuration of a latch circuit 10 according to a third embodiment of the present invention. In the flip-flop circuit 10 shown in FIG. 7 , the node voltage control circuits 1G and 1H are removed from the latch circuit 10 shown in FIG. 4 . The gates of the P-channel type MOS transistor MP2D and the gates of the N-channel type MOS transistors MN2B and MN1F are connected to the node N1E, and the gates of the P-channel type MOS transistors MP2A and MP1E and the gates of the N-channel type MOS transistor MN2C The gate is connected to node N2C.

[0073] Since in the latch circuit 10 shown in FIG. 7, transistors causing less noise influence are removed and nodes whose voltage variations are small are removed, the generation rate of soft errors increases compared with the circuit shown in FIG. 4, but has It ...

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Abstract

A latch circuit includes: first nodes which are three or more and to which a voltage in a first signal level is set; second nodes which are three or more and to which a voltage in a second signal level obtained by inverting the first signal level is set; and first node voltage control circuits having the first nodes; and second node voltage control circuits having the second nodes. Each of the first node voltage control circuits is connected with at least two of the three or more second nodes, and controls the voltage of the first node based on the voltages of the at least two second modes. Each of the second node voltage control circuits is connected with at least two of the three or more first nodes and controls the voltage of the second node based on the voltages of the at least two first nodes.

Description

technical field [0001] The present invention relates to a latch circuit and a trigger circuit using the latch circuit. Background technique [0002] In recent years, it has been known that soft errors are caused by high-energy radiation (Al emission lines and neutron beams) radiated to latch circuits. The soft error is a malfunction caused by a "single event disturbance (SEU)" in which data is inverted, which is caused by the phenomenon that Al emission lines and / or neutron beams are incident on the latch circuit to Charges are generated and collected by areas (nodes) for retaining data. The soft errors are transient failures, and if the correct data can be rewritten again, the latch circuit will work normally again. However, since the stored data is reversed even temporarily, there are cases where its influence acts on the entire computer system. [0003] Soft errors occurring in the conventional latch circuit shown in FIG. 1 will be illustrated as an example. FIG. 1 is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/037H03K3/356
CPCH03K3/356191H03K3/0375
Inventor 山本宽
Owner NEC ELECTRONICS CORP
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