The invention relates to a novel
silicon substrate
low resistance inductance structure and a
wafer level encapsulating method of the novel
silicon substrate
low resistance inductance structure, and belongs to the technical field of
semiconductor encapsulation. A coil groove (102) is formed in the upper surface of a
silicon wafer (100) in an
etching mode, an
insulation layer (300) is coated inside the coil groove (102), an
electroplating seed layer (300) is arranged in a deposit mode through a physical method, a thick
copper metal wiring layer (400), namely an
inductance coil, is formed in the coil groove (102) in a photoetching imaging mode through an
electroplating technology, and finally, a secondary passivating layer (500) and
metal leading wires (600) are arranged on the thick
copper metal wiring layer (400), and the thick
copper metal wiring layer (400) is communicated with the thick
copper metal wiring layer (400) through an secondary passivating layer opening (501). According to the novel silicon substrate
low resistance inductance structure and a
wafer level encapsulating method of the novel silicon substrate low resistance inductance structure, the
copper metal wiring layer serving as the inductance coil is embedded into the interior of a silicon substrate body, technological difficulty and technological cost of preparation of the inductance coil are reduced, an encapsulating density is improved, meanwhile
direct current resistance of an
inductor is reduced by increasing the thickness of coils, and a quality factor of the
inductor is improved.