103results about How to "Reduce capacitive load" patented technology

A stack package may include a substrate having first and second faces opposite each other and an opening formed therein. The first semiconductor chip may be mounted on the first face of the substrate and include a through electrode in the middle region of the first semiconductor chip that is exposed through the opening. The second semiconductor chip may be stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by the through electrode of the first semiconductor chip. The circuit pattern may be formed on the second face of the substrate and include a bonding pad arranged adjacent to the opening and electrically connected to the through electrode of the first semiconductor chip through the opening, an outer connection pad spaced apart from the bonding pad and a connection wiring extending from the opening to the outer connection pad via the bonding pad.

A flip-flop circuit includes a flip-flop, a first pass gate, a second pass gate, and a third pass gate. The first pass gate has an input to receive an input signal, an output coupled to the flip-flop's data input, and a control terminal to receive a first control signal. The second pass gate has an input coupled to the flip-flop's data input, an output coupled to the circuit's output, and a control terminal to receive a second control signal. The third pass gate has an input coupled to the flip-flop's data output, an output coupled to the circuit's output, and a control terminal to receive a third control signal. The first, second, and third control signals may be generated in response to various logical combinations of a bypass signal and a clock enable signal.

A light-emitting device has a plurality of data lines and a plurality of pixel circuits. Each of the plurality of pixel circuits includes a light-emitting element that has a first electrode and a second electrode and that emits light having an intensity depending on the amount of driving current; a driving transistor that supplies the driving current to the first electrode; a holding transistor that supplies a driving signal supplied via the data lines to the driving transistor; and a connecting line that connects the driving transistor to the holding transistor. The second electrode is formed in a region different from a region in which the data lines are formed such that the second electrode is not opposite to some or all of the data lines.

Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input / output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input / output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input / output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input / output buffers of the first chip, and the connection pads of the first chip and the second chip.

An electrosurgical system is disclosed. The system includes an electrosurgical instrument having at least one electrode configured as a first sensor for measuring a voltage drop therethrough and a temperature sensor for a thermal sensor configured to measure a temperature difference across the at least one electrode; and a generator including an output stage coupled to the at least one electrode, the output stage configured to generate radio frequency energy; and a controller configured to determine actual radio frequency current based on the voltage drop and electrical resistivity of the at least one electrode and radio frequency power based on the measured temperature difference and the thermal conductivity of the at least one electrode.

The invention discloses an inverter of a grid integrated driving circuit. The inverter comprises transistors T1v-T5v and a coupling capacitor C1v, a second electrode of the T1v and a second electrode of the T3v are connected with positive level VDD, a grid and a first electrode of the T1v are connected with a second electrode of the T2v, a grid of the T3v, a first electrode of the T5v and one end of the C1v, a grid of the T2v and a grid of the T4v are connected with a control signal, the grid and a second electrode of the T5v are connected with a feedback signal RSTv, a first electrode of the T2v and a first electrode of the T4v are connected with first negative level, a second electrode of the T3v and a second electrode of the T4v are connected with the other end of the C1v, and an output node QBv of the inverter is formed. The invention further discloses the grid integrated driving circuit with the inverter and a driving method of the grid integrated driving circuit. The inverter is low in power consumption and noise and excellent in anti-jamming capability, and the output pull-up transistors and the inverter are rapid in action and can work under high frequency.

An oscillator circuit and system are provided having a peak detector that can determine a peak voltage value from the oscillator. The peak voltage value can then be compared against a predetermined voltage value by a controller coupled to the peak detector. The comparison value is then used to change a bias signal if the peak voltage value is dissimilar from the predetermined voltage value. A variable capacitor or varactor can be formed from a transistor and is coupled to the oscillator for receiving the bias signal upon a varactor bias node. The bias signal is used to regulate the capacitance within the varactor as applied to the oscillator nodes. Another controller can also be coupled to the peak detector to produce a second bias signal if the peak voltage is dissimilar from a second predetermined voltage value. The second bias signal can then be forwarded into an amplifier having a variable gain to regulate the gain applied to the oscillator. The combination of a varactor and variable gain amplifier regulate the negative resistance applied to the resonating circuit during startup and steady state operations to ensure a relatively fast startup, and to maintain optimal loading and accurate steady state amplitude after startup has completed.

Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input / output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input / output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input / output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input / output buffers of the first chip, and the connection pads of the first chip and the second chip.

Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input / output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input / output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input / output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input / output buffers of the first chip, and the connection pads of the first chip and the second chip.

On the first storage device side, when data is written in a first volume, a journal of such data is transmitted to a second storage device; on the second storage device side, a snapshot of a second volume and the respective journals are stored; on the second storage device side, the first volume is rebuilt at a rebuilding time according to a rebuilding order; on the second storage device side, data of an address rewritten from the rebuilding time onward is transmitted as difference data to the first storage device; and on the first storage device side, the first volume is rebuilt at the rebuilding time based on the difference data.

A method of forming a self-aligned SOI diode, the method comprising depositing a protective structure over a substrate; implanting a plurality of diffusion regions of variable dopant types in an area between at least one pair of isolation regions in the substrate, the plurality of diffusion regions separated by a diode junction, wherein the implanting aligns an upper surface of the diode junction with the protective structure; and removing the protective structure. The method further comprises forming a silicide layer over the diffusion regions and aligned with the protective structure. The protective structure comprises a hard mask, wherein the hard mask comprises a silicon nitride layer. Alternatively, the protective structure comprises a polysilicon gate and insulating spacers on opposite sides of the gate. Furthermore, in the removing step, the spacers remain on the substrate.

A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON / OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring. As a result, reduction of a parasitic capacitance of the wiring, reduction in the number of elements, reduction in the size of an amplitude of an input signal, etc. in the signal line driving circuit are attained.

In a particular illustrative embodiment, a circuit device that includes first logic and second logic is disclosed. The first logic receives a clock signal and a first portion of a memory address of a memory array, decodes the first portion of the memory address, and selectively applies the clock signal to a selected group of wordline drivers associated with the memory array. The second logic decodes a second portion of the memory address and selectively activates a particular wordline driver of the selected group of wordline drivers according to the second portion of the memory address.

A plurality of sequential nodes in a design file for an electronic device are identified and one or more combinatorial power metric values are computed for the plurality of sequential nodes based upon an effective switching capacitance, a switching activity measure, and a power effort measure for at least a first device downstream from the each sequential node at a specified depth. The combinatorial power metric values for the plurality of sequential node are stored and compared to a target power metric value to determine if power consumption at the electronic device meets a predetermined power performance goal.

Provided are a thin film transistor array substrate, a manufacturing method and a liquid crystal display panel. The thin film transistor array substrate comprises a substrate, a first metal layer, a first insulation layer, an active layer, a second metal layer, a second insulation layer, a third metal layer, a third insulation layer and a pixel electrode. The first metal layer is formed on the substrate and comprises a scanning line and a grid. The first metal layer is covered with the first insulation layer, and the active layer is formed on the first insulation layer. The second metal layer is formed on the first insulation layer and comprises a source electrode and a drain electrode. The second metal layer is covered with the second insulation layer, and a first contact hole and a second contact hole are formed in the second insulation layer. The third metal layer is formed on the second insulation layer and comprises a data line and a conductive block, the data line is connected with the source electrode through the first contact hole, and the conductive block is connected with the drain electrode through the second contact hole. The third metal layer is covered with the third insulation layer, and a third contact hole is formed in the third insulation layer. The pixel electrode is formed on the third insulation layer, and the pixel electrode is connected with the conductive block through the third contact hole.

The power consumption of a shift register or a display device including the shift register is reduced. A clock signal is supplied to a shift register by a plurality of wirings, not by one wiring. Any one of the plurality of wirings supplies a clock signal in only part of the operation period of the shift register, not during the whole operation period of the shift register. Therefore, the capacity load caused with the supply of clock signals can be reduced, leading to reduction in power consumption of the shift register.