A parallel
data interface and method is provided herein, which adjusts a timing relationship of a
clock signal to not only minimize
clock skew, but to also compensate for
noise components that may affect one or more paths of a parallel data
bus. In some embodiments, the parallel
data interface includes a first phase generator coupled to generate a first plurality of time
delay pulses, and a first phase selector adapted to select one of the first plurality of time
delay pulses to adjust the timing of a
clock signal to sample each and every one of the plurality of data signals between minimum setup and
hold time thresholds. In some embodiments, the parallel
data interface includes a second phase generator coupled to generate a second plurality of time
delay pulses, and a second phase selector adapted to select one of the second plurality of time delay pulses to adjust the timing of the
clock signal to output the plurality of data signals from the data interface at least an amount of time (i.e., an
access time) after the adjusted
clock transition is output from the data interface.