Method and apparatus for reducing power consumption

Abstract

An arrangement for clock control in a device receiving a clock from an external source includes switching means (101) for switching an external clock through to the device as an internal clock, and clock request generation means (102, 103), adapted to switch clock signal through to the external clock controller as requests for suppressing and restarting the external clock. Control means (104) are provided in the form of a state machine to control the generation of the internal clock through the switching means, and to control the clock request generation means in accordance with a predetermined state of two signals, one generated internally by the device, the other by the external clock controller (20). The clock request generation means are also coupled to a clock start module adapted to receive several input signals (12) for signalling an event requiring the clocked operation of the device.

Description

technical field [0001] The present invention relates to a method and arrangement for deactivating and restarting a clock in a device. The invention particularly relates to devices, such as battery powered devices, which require that clock generation be suppressed during periods of inactivity to reduce power consumption. Background technique [0002] In battery powered products, such as mobile phones or portable personal computers, it is important to conserve power in order to extend battery life. One way to reduce power is to turn off the processor clock during periods of inactivity. However, in products that need to operate synchronously with an external device, such as a mobile phone that must be synchronized with a network, at least one clock must be running continuously to provide this synchronization. In a product containing several processors, one processor is usually designated as the master processor relative to one or several slave processors in t...

AI Technical Summary

Problems solved by technology

[0004] One problem with this circuit is that reaching an asynchronous interrupt while the external clock is inhibited can cause the internal clock to switch and possibly cause the processor circuit to enter a disabled state

A further disadvantage of the described circuit is that the clock control device can only handle one interrupt, which severely limits its application

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