32 results about "Scalable design" patented technology

A data validation architecture is provided that minimizes duplicate code and enables easy creation of new validations using a high-performance and scalable design. Such an architecture provides sufficient flexibility to disable certain validations when they are not applicable to the flow, interpret validation failures differently according to requirements of the calling application, and specify the type of document for which a particular validation is applicable. The architecture provides a standardized flow for performing data validation, specifying a set of required parameters for validation subroutines, as well as where validation results are to be stored for access by a calling program. Such an architecture also provides a framework for performing common processing required for most validation flows without restricting the flexibility of the validation subroutines.

A system and method for assigning certificates and reducing the size of the certificate revocation lists in a PKI based architecture for a vehicle wireless communications system that includes separating a country, or other area, into geographic regions and assigning region-specific certificates to the vehicles. Therefore, a vehicle need only process certificates and certificate revocation lists for the particular region that it is traveling in. Vehicles can be assigned multiple certificates corresponding to more than one region in the vehicles vicinity as advance preparation for possible travel or transmission into nearby regions. Further, the expiration time of certificates assigned to vehicles corresponding to a given geographic region can be tailored to be inversely proportional to the distance from a registered home region of the vehicle. A scalable design for a back-end certifying authority with region-based certificates can also be provided.

The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path delays of many components in existing implementations grow quadratically with the issue width and the window size. This patent presents a novel way to reimplement these components and reduce their critical-path delay growth. It then describes an entire processor microarchitecture, called the Ultrascalar processor, that has better critical-path delay growth than existing superscalars. Most of our scalable designs are based on a single circuit, a cyclic segmented parallel prefix (cspp). We observe that processor components typically operate on a wrap-around sequence of instructions, computing some associative property of that sequence. For example, to assign an ALU to the oldest requesting instruction, each instruction in the instruction sequence must be told whether any preceding instructions are requesting an ALU. Similarly, to read an argument register, an instruction must somehow communicate with the most recent preceding instruction that wrote that register. A cspp circuit can implement such functions by computing for each instruction within a wrap-around instruction sequence the accumulative result of applying some associative operator to all the preceding instructions. A cspp circuit has a critical path gate delay logarithmic in the length of the instruction sequence. Depending on its associative operation and its layout, a cspp circuit can have a critical path wire delay sublinear in the length of the instruction sequence.

A register file apparatus and method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

A free vehicle suitable to serve as a platform to carry a variety of equipment to the ocean floor, actuate devices at the floor and at intermediate points on the way to and returning from the ocean floor is described. The free vehicle includes standardized power, control electronics, navigation equipment and mechanical release mechanisms that can be used in conjunction with custom experiments. Exemplary experiments include sensors and sampling equipment used for deep-sea exploration. The free vehicle platform provides for scalable designs to meet scientific needs and surface vessel constraints.

A refrigerant storage device that arranges two end plates to form a cavity and includes a turbulator plate within the cavity. The turbulator plate is arranged within the cavity to reinforce the cavity by providing a plurality of reinforcement portions between the end plates. The cavity is sized and the turbulator plate is configured so a liquid portion of refrigerant flowing through the cavity collects onto the turbulator plate. The device has a rectangular shape that simplifies vehicle packaging and allows the device to be readily integrated into a plate-type refrigerant-to-liquid coolant heat exchanger. The device is formed by a stacking arrangement of parts that provides for a readily scalable design.

The invention discloses an active antenna related device, a system and a sending and receiving calibration method, which are used to realize the scalable design of the antenna array, reduce the difficulty of engineering implementation and provide engineering implementation reliability. The active antenna device includes: N active antenna arrays, a main calibration coupling circuit unit, a transceiver calibration unit, a calibration parameter storage unit, and an optical radio communication ROF photoelectric conversion unit, wherein the N is greater than 1; the active antenna array At least including an antenna coupling circuit unit and M antenna elements connected to the antenna coupling circuit unit, where M is greater than 1; the antenna calibration coupling circuit unit of the active antenna array is connected to the main calibration coupling circuit through a calibration channel unit, the main calibration coupling circuit is connected to the transceiver calibration unit, and the transceiver calibration unit and the calibration parameter storage unit are respectively connected to the ROF photoelectric conversion unit.