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1699results about How to "Avoid performance" patented technology

Method and apparatus for illuminating a field-of-view and capturing an image

A variable illuminator, for instance a device for scanning a beam of light, emits a selected amount of power to a plurality of spots across a field of view. The amount of power is determined as inversely proportional to the apparent brightness of each spot. In the case where the spot size is equal to pixel size, the device may operate with a non-imaging detector. In the case where pixel size substantially equals spot size, the output of the variable illuminator may be converged to produce a substantially uniform detector response and the image information is determined as the inverse of a frame buffer used to drive the variable illuminator. The illuminator and detector may be driven synchronously. In the case where an imaging detector is used, the variable illumination may be used to compress the dynamic range of the field of view to substantially within the dynamic range of the imaging detector.
Owner:MICROVISION

Cycle segmented prefix circuits

The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path delays of many components in existing implementations grow quadratically with the issue width and the window size. This patent presents a novel way to reimplement these components and reduce their critical-path delay growth. It then describes an entire processor microarchitecture, called the Ultrascalar processor, that has better critical-path delay growth than existing superscalars. Most of our scalable designs are based on a single circuit, a cyclic segmented parallel prefix (cspp). We observe that processor components typically operate on a wrap-around sequence of instructions, computing some associative property of that sequence. For example, to assign an ALU to the oldest requesting instruction, each instruction in the instruction sequence must be told whether any preceding instructions are requesting an ALU. Similarly, to read an argument register, an instruction must somehow communicate with the most recent preceding instruction that wrote that register. A cspp circuit can implement such functions by computing for each instruction within a wrap-around instruction sequence the accumulative result of applying some associative operator to all the preceding instructions. A cspp circuit has a critical path gate delay logarithmic in the length of the instruction sequence. Depending on its associative operation and its layout, a cspp circuit can have a critical path wire delay sublinear in the length of the instruction sequence.
Owner:YALE UNIV

DMA engine for protocol processing

InactiveUS20060206635A1Determinism and uniformity in operationPredictable performance gainElectric digital data processingData transmissionProtocol processing
A DMA engine, includes, in part, a DMA controller, an associative memory buffer, a request FIFO accepting data transfer requests from a programmable engine, such as a CPU, and a response FIFO that returns the completion status of the transfer requests to the CPU. Each request includes, in part, a target external memory address from which data is to be loaded or to which data is to be stored; a block size, specifying the amount of data to be transferred; and context information. The associative buffer holds data fetched from the external memory; and provides the data to the CPUs for processing. Loading into and storing from the associative buffer is done under the control of the DMA controller. When a request to fetch data from the external memory is processed, the DMA controller allocates a block within the associative buffer and loads the data into the allocated block.
Owner:PMC-SIERRA

Storage Controller and Duplicated Data Detection Method Using Storage Controller

A storage controller of the present invention narrows down the target for data comparison by comparing hash codes beforehand and rapidly detects duplicated data. A hash value setting unit sets a hash code in data received from a host. Hash code-attached data is stored in a logical volume. A microprocessor unit compares the hash codes for each comparison-targeted data. When hash codes match with one another, a data comparator compares the target data, and determines whether or not the data is duplicated data. When duplicated data is detected, the microprocessor unit removes the duplicated data.
Owner:HITACHI LTD

Relay system and method for cellular communication

A relay method is disclosed in a cellular communication system including an access node for providing an access service using resources of a licensed band to a particular terminal among a plurality of terminals with a partial licensed band of the full frequency spectrum, and a relay station for relaying communication between the terminal and an access node. The relay method includes performing base station-led resource allocation on a licensed band for a terminal and a relay station located in a service area of the base station, and performing relay station-led resource allocation on the licensed band and an unlicensed band for a terminal located in a service area of the relay station.
Owner:SAMSUNG ELECTRONICS CO LTD

Wireless transmitter and precoding method

InactiveUS20110286502A1Decrease of data ratePrevent error rate performanceMultiple-port networksDelay line applicationsError ratioDecomposition
Disclosed is a wireless transmitter that can prevent deterioration of the error rate characteristic without reducing the data rate during mobile communications also utilizing THP for FDE. In the device, an equivalent channel matrix computation unit (118) computes weights to be used for FDE of a transmission block and an equivalent channel matrix indicating equivalent channels that are generated from channel impulse responses, and a decomposition unit (119) obtains a lower triangular matrix (L), that consists of a diagonal element that includes a high channel quality at the front of the transmitting block and a low channel quality at the rear, so as to indicate the channel quality of the transmission block, and an element indicating interference with the transmission block, and a unitary matrix (Q) by means of LQ decomposition of the equivalent channel matrix. A computation unit (120) uses the lower triangular matrix (L) and the average channel quality to compute a matrix (B) that minimizes the mean square error of all symbols between the transmission block before precoding and a block received by a wireless receiver. A preceding unit (103) performs THP of the transmission block using the matrix (B).
Owner:PANASONIC CORP

System and method of adaptive frequency hopping with look ahead interference prediction

A novel and useful adaptive frequency hopping scheme for wireless devices and networks operating in a congested environment of similar devices, where capacity maximization is desired. The hopping sequence of each wireless link is dynamically adapted such that the impact of the surrounding interference is minimized and the interference induced onto the coexisting systems is also minimized. The scheme detects the repetitive presence of interference on a particular channel and comprises a replacement mechanism for swapping the interfered frequency-channel with one that would be clear for that particular time-slot. The mechanism detects interference during a redundant portion of the transmission (i.e. header or trailer) without having to experience packet failures (i.e. data loss). If the interference impact (e.g. corrupted header bits) exceeds a predefined threshold, that frequency channel is declared temporarily unusable for that time slot and is replaced with another in accordance with a frequency replacement policy. Periodic interference at a particular frequency, originating from a coexisting system of similar operating parameters, may also be detected at instances that are distant from the timeslots for which that particular frequency is to be used, such that frequency replacement in the hopping sequence can be scheduled ahead of time and collisions would be avoided altogether.
Owner:TEXAS INSTR INC

Aerial delivery device

InactiveUS20050230555A1Reduce dragPerformance be not hinderParachutesLaunching weaponsGuidance systemDrogue parachute
A guided aerial delivery device which can be used to safely and accurately deliver a payload and supplies from an aircraft in flight to a specific target location in a reduced time. The aerial delivery device uses an overloaded ram-air drogue parachute controlled by a guidance system to steer the payload towards the intended target. When a selected altitude is reached, a recovery parachute is activated and the payload descends the remaining distance under the recovery parachute.
Owner:STRONG EDWARD

Car connected to at least one trailer and backward motion control method

A car connected to at least one trailer and backward motion control method are provided. The car includes a driving part controlling a velocity and a direction of the car, a backward-motion control terminal outputting a first backward-motion control signal corresponding to a backward velocity and a backward direction of the last trailer according to a user's operation, a control signal converter converting the first backward-motion control signal to a second backward-motion control signal which corresponds to a backward velocity and a backward direction of the car and makes the last trailer move backward as the backward velocity and the backward direction corresponding to the first backward-motion control signal, and a backward-motion controller controlling the driving part on the basis of the second backward-motion control signal so that the last trailer moves backward by the backward velocity and the backward direction corresponding to the first backward-motion controlling signal.
Owner:KOREA UNIV RES & BUSINESS FOUND

Translation lookaside buffer for virtual memory systems

The basic idea comprised of the present invention is to provide a translation lookaside buffer (TLB) arrangement which advantageously uses two buffers, a small first level TLB1 and a larger second level TLB2. The second level TLB feeds address information to the first level TLB when the desired virtual address is not contained in the first level TLB. According to the invention the second level TLB is structured advantageously comprising two n-way set-associative sub-units of which one, a higher level unit covers some higher level address translation levels and the other one, a lower level unit, covers some lower level translation level. According to the present invention, some address information holds some number of middle level virtual address (MLVA) bits, i.e., 8 bits, for example, being able to serve as an index address covering the address range of the higher level sub-unit. Thus, the same information is used as a tag information in the lower-level sub-unit and is used herein as a quick reference in any look-up operation in order to find the absolute address of the concerned virtual address. Further, the commonly used status bits, like; e.g., valid bits, are used in both TLB structures, too.
Owner:IBM CORP
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