Patents
Literature
Hiro is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Hiro

80results about How to "Prevent electrical short circuit" patented technology

Light emitting device having plurality of light emitting cells and method of fabricating the same

A light emitting device having a plurality of light emitting cells is disclosed. The light emitting device comprises a substrate; a plurality of light emitting cells positioned on the substrate to be spaced apart from one another, each of the light emitting cells comprising a p-type lower semiconductor layer, an active layer and an n-type upper semiconductor layer; p-electrodes positioned to be spaced apart from one another between the substrate and the light emitting cells, the respective p-electrodes being electrically connected to the corresponding lower semiconductor layers, each of the p-electrodes having an extension extending toward adjacent one of the light emitting cells; n-electrodes disposed on upper surfaces of the respective light emitting cells, wherein a contact surface of each of the n-electrodes electrically contacting with each light emitting cell exists both sides of any straight line that bisects the light emitting cell across the center of the upper surface of the light emitting cell; a side insulating layer for covering sides of the light emitting cells; and wires for connecting the p-electrodes and the n-electrodes, the wires being spaced apart from the sides of the light emitting cells by the side insulating layer.
Owner:SEOUL SEMICONDUCTOR

Production method for electric device assembly and electric device assembly

Cell-to-cell connection plates (1) each integrally having a welding part (2) shaped to fall within a circular end of a battery case (7) and a connecting part (2) extending from this welding part (2) are provided. The cell-to-cell connection plates (1) are attached to one electrode terminal and the other electrode terminal of the battery case (7) by welding the welding parts (2), respectively. The connecting parts (3) of the respective cell-to-cell connection plates (1) attached to each adjoining pair of cylindrical batteries (Ba) are overlapped with each other and coupled into electric connection. Consequently, regardless of whether a plurality of cylindrical batteries (Ba) are axially arranged in series or radially juxtaposed, each adjoining two can be connected to each other by using the identical cell-to-cell connection plates (1) for cost reduction. It is also possible to provide a sufficient heat dissipation effect and achieve sufficient robustness and weight saving even when connecting large-sized cylindrical batteries.
Owner:PANASONIC CORP

Method for fabricating an array substrate for a liquid crystal display device

The present invention relates to a method for fabricating an array substrate for a liquid crystal display device, using an etchant composition for a copper-based metal film, wherein the etchant composition comprises, based on the total weight of the etchant composition: a) 2 to 30 wt % of hydrogen peroxide (H2O2); b) 0.1 to 5 wt % of nitric acid (HNO3); c) 0.01 to 1.0 wt % of a fluorine compound; d) 0.1 to 5 wt % of an azole compound; e) 0.1 to 8.0 wt % of an imidazole compound; and f) the remainder being water.
Owner:DONGWOO FINE CHEM CO LTD

Active matrix substrate and its manufacturing method

An active matrix substrate with a high aperture ratio is provided, which is capable of preventing electrical short circuits between pixel electrodes and auxiliary capacitive electrodes. Gate lines and auxiliary capacitive electrodes are formed on an insulated substrate. The auxiliary capacitive electrodes have holes formed therethrough. To cover the gate lines and the auxiliary capacitive electrodes, a first interlayer insulating film is formed, on which source lines, a semiconductor layer, and drain electrodes are formed. Then, a second interlayer insulating film is formed to cover all those layers. In the second interlayer insulating film, contact holes are formed to reach the drain electrodes in areas corresponding to the areas of the holes. Pixel electrodes formed on the second interlayer insulating film are connected to the drain electrodes through the contact holes.
Owner:TRIVALE TECH

Semiconductor device and wire bonding method used for the same

PROBLEM TO BE SOLVED: To prevent the occurrence of electric short circuits between the most closely arranged wires out of a plurality of wires for connecting individual groups of electrode pads of a semiconductor chip and two leads arranged adjacent to each other around the semiconductor chip, respectively.SOLUTION: In the semiconductor device 1, second bonds of each three wires 11-13 and 15-17 of each lead 7 and 9 are arranged in the longitudinal direction of the leads 7 and 9. The three first wires 11-13 connected to one lead 7 are connected to the electrode pads 19-21 in a first row arranged in the arranging direction of the leads 7 and 9, while the three second wires 15-17 connected to the other lead 9 are connected to the electrode pads 23-25 in a second row arranged further away from the leads 7 and 9 than those in the first row. The first wire 13 connected to the most posteriorly located second bond of the lead 7 is connected to other electrode pad 20 in the first row than the electrode pad 21 in the first row which is closest to the electrode pads 23-25 in the second row.
Owner:YAMAHA CORP

Semiconductor package with electrical connection structure and manufacturing method thereof

The invention provides a semiconductor package with an electrical connection structure and a manufacturing method thereof, and the semiconductor package comprises a conducting wire layer, a chip, a welding wire, a packaging colloid, an anti-welding layer and welding balls, wherein the conducting wire layer comprises a chip carrier and a plurality of conducting wires annularly arranged on the periphery of the chip carrier; the packaging colloid comprise a plurality of recesses which are used for embedding the chip carrier and the conducting wires, in the depth of greater than the thickness of the chip carrier and the conducting wires and further exposed on the surface of the conducting wires and the chip carrier; the anti-welding layer is formed in the recesses of the packaging colloid, and the anti-welding layer comprises a plurality of open holes of the anti-welding layer for exposing all conducting wire terminals and part of the chip carrier; and the welding balls are formed in all the open holes of the anti-welding layer to electrically connect with the corresponding conducting wire terminals. Therefore, the adhesion strength of the anti-welding layer is improved by mutual embedding and clamping between the anti-welding layer and the packaging colloid, a path for enabling wet gas to infiltrate into the package is prolonged, and the product reliability is enhanced.
Owner:SILICONWARE PRECISION IND CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products