39results about How to "Less control signal" patented technology

In an imaging device including imaging elements, a driver configuration which does not require much layout space and ensures a reduced number of wirings is provided. The imaging device includes imaging elements 1 arranged in a matrix or in lines and a single driver circuit 6 disposed along the vertical direction of the matrix or along the direction in which the lines extend to control the driving of the imaging elements 1. Then, the driver circuit 6 serves the double function of a reset driver adapted to reset the imaging elements and a read driver adapted to read out the signals from the imaging elements.

The present invention provides a control circuit, including a current source module, a conversion module and a first comparison module: the current source module is used to generate a current signal whose magnitude is positively correlated with temperature; the conversion module includes a first conversion unit and / or a second conversion unit , the first conversion unit is used to provide the first voltage signal to the positive input terminal of the first comparison module, and the first voltage signal is positively correlated with the magnitude of the current signal generated by the current source module; the second conversion unit is used to provide the first comparison module The reverse input terminal of the module provides a second voltage signal, and the second voltage signal is negatively correlated with the magnitude of the current signal generated by the current source module; the first comparison module is used to output control when the positive input terminal is greater than the voltage signal of the reverse input terminal signal, the control signal is negatively correlated with the voltage signal difference between the positive input terminal and the negative input terminal of the first comparison module. Correspondingly, the invention also provides a backlight driving device and a display device, and the invention can prevent the temperature of the display device from being too high.

When chip is in stand by mode, system operation timer of the chip is closed so that each module in the chip stops working. Control is started up under slow timer to maintain save mode so as to reach purpose of reducing power consumption and saving electricity. In order to keep synchronization to base station when save mode exits, the invention designs a calculation method to keep good synchronization to base station when save mode exits, and to possess very small frequency deviation. Comparing with prior art, the invention possesses advantages of few control signals, easy of implementation, controllable time in save mode, and small frequency deviation.

The invention discloses a time-analog switching circuit and a single photon flight time measuring method. The time-analog switching circuit comprises a signal input logic unit, a timing unit, a voltage holding unit and a read out unit; the signal input logic unit converts a photon signal into a logic electrical level, and the input end of the signal input logic unit correspondingly receives the photon signal, a start signal and a stop signal, and the output end of the signal input logic unit is connected with the input end of the timing unit; the timing unit includes a current mirror structureproviding a stable charging current, a current mirror structure providing a current source and a timing capacitor, and a voltage of an electrode plate of the timing capacitor linearly increases withtime after the timing capacitor starts counting; the voltage holding unit is used for holding the voltage of the electrode plate of the timing capacitor, the input end of the voltage holding unit is connected with the output end of the timing unit, the output end of the voltage holding unit is connected with the read out unit, and the read out unit reads out a voltage signal of the electrode plate. According to the time-analog switching circuit and the single photon flight time measuring method, the manufacturing process is compatible with the CMOS process, the manufacturing cost is low, and the rate of finished products is high; and meanwhile, the time-analog switching circuit has the advantages of high filling factors, high resolution and a large measuring range.

The invention discloses a melon and fruit picking device and a picking method thereof, which relate to the technical field of agricultural equipment. The melon and fruit picking device comprises a clamping device, a cutting device and a control device, wherein the clamping device comprises a step motor, a driven gear, a left support swinging rod, a left finger, a driving gear, a right support swinging rod, a right finger and supporting blocks, the supporting blocks are arranged under the left finger and the right finger, the driving gear and the step motor are connected, the driving gear and the driven gear are connected through a gear pair, the left finger is arranged at the end parts of the left support swinging rod and the driven gear, the right finger is arranged at the end parts of the right support swinging rod and the driving gear, the cutting device comprises a cutter, a swinging air cylinder and an electromagnetic reversing valve, the cutter is arranged on an output shaft of the swinging air cylinder, the electromagnetic reversing valve is arranged on the swinging air cylinder, the swinging air cylinder is arranged on a cutter frame, and the cutter frame is arranged on a back seat vertically and fixedly arranged on a base. The melon and fruit picking device and the method can be used for automatically picking melons and fruits, and a large amount of time and labor canbe saved for laborers.

The invention discloses an X-shaped ferroelectric memory array structure which belongs to the integrated circuit design manufacturing technical field. The array structure of the invention takes X-shaped ferroelectric memory cells as basic components, wherein, each ferroelectric memory cell respectively shares a control line CL with memory cells in the same row or the same column in the horizontal-vertical direction; the memory cells in the same column shares a data signal line BL in the column direction; the memory cells in the same row shares a BL in the row direction; rows and columns do notshare BLs. The X-shaped ferroelectric memory array structure is based on a data storage and read-write mechanism of a ferroelectric memory and borrows ideas from partial principles and read-write means of an FeRAM incorporated PL array architecture, thereby control and data read-write of the memory cells can be simultaneously performed along the row direction and the column direction and parallelread-write of multi-bit data can be easily realized; the symmetry of circuits and the arrangement of peripheral circuits are optimized; the number and the scale of decoding and drive circuits are reduced; moreover, the length of the BL line can be reduced and then the read-write speed is improved.

The invention provides a two-wire multiplexing circuit, which relates to the technical field of communication circuits. It includes a magnetic coupling isolation circuit, a first communication circuit and a second communication circuit, the output end of the magnetic coupling isolation circuit is connected to the input end of the first communication circuit, and the output end of the first communication circuit is connected to the input end of the second communication circuit. There is no need to send or receive control conversion signal lines, which saves output or input interfaces, saves costs, and improves data transmission efficiency.

The invention discloses an SRAM storage unit and a memory, relates to the technical field of circuit design, and is used for improving data security and reducing the area and power consumption of the SRAM memory. The SRAM storage unit includes: a data latch circuit, a first switch circuit, a second switch circuit, a third switch circuit and a storage circuit. The data latch circuit has a first output terminal, a second output terminal and a switching node. The first switch circuit is connected in series between the second output terminal and the conversion node. The second switch circuit is connected in series between the first output terminal and the first terminal of the storage circuit. The third switch circuit is connected in series between the conversion node and the first terminal of the storage circuit. The second end of the storage circuit is electrically connected to the ground end. The SRAM memory includes the SRAM storage unit mentioned in the above technical solution.

The invention discloses a CMOS full-digital BPSK modulation pulse radio ultra-wideband transmitter, which is composed of a BPSK modulation module, a delay generation module, a pulse sequence generation module and an antenna; the BPSK modulation module processes the input digital signal DATA and the clock signal CLK, Generate a digital signal that meets the requirements of BPSK modulation; the delay generation circuit of each stage of the delay generation module uses the characteristics of inverter delay to delay the modulated signal output by the BPSK modulation module to obtain different delay outputs, which are used to control the corresponding The pulse sequence generating circuit of the device generates a pulse unit of equal time width; each stage of the pulse sequence generating circuit of the pulse sequence generating module generates a single pulse signal, and all the pulse signals are combined into a pulse sequence as the output signal output via the antenna. The wireless transmission signal generated by the invention meets the requirements of the frequency spectrum and working frequency band of UWB.

The invention discloses a half-rate clock data recovery circuit based on phase selection interpolation. The purpose is to solve the problem that the phase selection interpolation circuit for generating a pair of adjustable quadrature clock signals in the existing structure is too complicated, and proposes a A combination method of a novel phase-selective interpolation circuit. The half-rate clock data recovery circuit based on the phase selection / interpolation type includes a half-rate Bang-Bang type phase detector, a phase selector, a phase interpolator, a digital filter, a digital controller and an outer ring reference clock, and the phase selection Compared with the original structure, the interpolation circuit uses a group of phase selection circuits. While ensuring the generation of a pair of adjustable quadrature clock signals, the scale of the circuit is reduced, thereby reducing the area of ​​the subsequent layout and reducing the power of the overall circuit. consumption.

The invention relates to a flash lamp control circuit, which can control the illumination according to the sensitive voltage and preset voltage. Said control circuit is formed by the first comparer, the second comparer and a logic gate; or formed by a comparer, the first reverse device, the first crystal tube, the first logic gate and the second logic gate. The invention can instantly discharge the capacitor without additional control signal when the trigger signal is stopped. And it can also comprise a clamp circuit, which can clamp the sensitive voltage lower than preset voltage according toa full-flash signal.