358results about How to "Improve layout efficiency" patented technology

The objective of this invention is to provide a head substrate capable of integrating driver transistors while keeping the size small even at high nozzle density, and integrating a functional circuit such as a temperature sensor or energy adjustment circuit. To achieve this, an ink supply port, a heater array which is arrayed along the longitudinal direction of the ink supply port and includes a plurality of heaters, a transistor array which is arrayed along the arrayed direction of the heater array and includes a plurality of transistors for driving a plurality of heaters, and a logic circuit which drives the transistor array are arranged on a head substrate. The logic circuit is arranged between the heater array and the transistor array.

The invention discloses a monitoring equipment layout method and device and belongs to the field of monitoring. The method comprises: establishing a two-dimensional coordinate system according to basic data input by a user, and receiving a region that needs to be monitored, which is divided by a user, through the two-dimensional coordinate system; converting two-dimensional coordinate data in the two-dimensional coordinate system into three-dimensional coordinate data; calculating a region covering range of the region that needs to be monitored, an actual scene and a horizontal coverage area of the region that needs to be monitored; screening at least one group of monitoring equipment meeting rules from a pre-set specialist rule base according to the region covering range of the region that needs to be monitored, the actual scene and the horizontal coverage area of the region that needs to be monitored; determining the conformity of each group of the monitoring equipment in the screened monitoring equipment group, and determining an optimal monitoring equipment group; and calculating an optimal monitoring layout scheme of the optimal monitoring equipment group. With the adoption of the monitoring equipment layout method and device, the optimal layout scheme can be rapidly, directly and accurately simulated, so that the excessive dependence on the technological level and experiences of constructors is avoided; and the quality of projects can be ensured and the layout efficiency can be improved. Moreover, the monitoring equipment can be sufficiently utilized and the cost is saved.

In order to do away with the need for a power source switching operation, and to improve motor regeneration charge efficiency in a hybrid vehicle, a one-way clutch is provided between an internal combustion engine and an electric drive motor.

An electric connection box includes a first cover and a second cover each having connector mounting portions, a first wiring board and a second wiring board which are mounted in a stacked manner between the first and second covers, a plurality of press-contacting terminals which are disposed in the connector mounting portions of the first and second covers, and are inserted in the first and second wiring boards, and a connecting wire which is selectively connected to the press-contacting terminals, and is arranged to extend over the first and second wiring boards when the first and second wiring boards are stacked together.

A detection device includes a drive circuit of a physical quantity transducer, a synchronization signal output circuit, and a detection circuit that performs detection of a physical quantity signal based on a physical quantity. The synchronization signal output circuit includes a delay locked loop (DLL) circuit that includes: a delay control circuit that outputs a delay control signal and a delay circuit that includes a plurality of delay units in which a delay time is controlled by the delay control signal; an adjustment circuit that includes at least one delay unit in which a delay time is controlled by the delay control signal, and outputs a signal obtained by delaying an input signal based on the output signal from the drive circuit to the DLL circuit; and an output circuit that outputs the synchronization signal based on multi-phase clock signals from the DLL circuit.

The invention relates to a surface mounting method for a printed circuit board, wherein the printed circuit board is provided with a large device including a large device body and a soldering pin. The method comprises the following steps: (1) obtaining an empty board including a first face and a second face, the first face being provided with a large device mounting area including a bonding pad area and a blank area; (2) a first side printing: printing solder paste in the bonding pad area; (3) gluing and the first face mounting: putting an adhesive in the blank area to form an adhesive layer and then mounting the large device on the large device mounting area; (4) reflow soldering: subjecting the mounted large device to reflow soldering; (5) second face treatment: subjecting the second face to conventional printing, patch mounting and reflow soldering. The method solves the dropping of the large device in the first face, does not need to increase the size of the PCB, reduces the production cost, improves the PCB layout efficiency, and is simple and convenient for industrial application.

A head substrate is capable of integrating driver transistors while keeping the size small even at high nozzle density, while integrating a functional circuit such as a temperature sensor or energy adjustment circuit. An ink supply port, a heater array which is arrayed along the longitudinal direction of the ink supply port and includes a plurality of heaters, a transistor array which is arrayed along the arrayed direction of the heater array and includes a plurality of transistors for driving a plurality of heaters, and a logic circuit which drives the transistor array are arranged on the head substrate. The logic circuit is arranged between the heater array and the transistor array.

The invention discloses a network topology layout method. The method comprises the steps of: fragmenting and dividing the network into a plurality of block networks; respectively carrying out topological layout on the ring sub-network and the chain / tree sub-network in each block network, dividing levels based on service characteristics of network elements, determining position information of eachnetwork element of each level of the ring sub-network according to a force steering algorithm, and carrying out layer-by-layer layout to construct a network topology of the ring sub-network; and taking the root node of each chain / tree-shaped sub-network as an initial position, determining the positions of the nodes on the chain of the chain / tree-shaped sub-network based on a force steering algorithm, carrying out layer-by-layer layout, and constructing the network topology of each chain / tree-shaped sub-network. Correspondingly, the invention further discloses a network topology layout system.According to the invention, the stable network topology can be rapidly obtained.

A three-state content addressable memory (CAM) cell comprising a pair of static random access memory (SRAM) cells each including a pair of cross-connected inverters for storing data values, and a pair of inverters for An access device for accessing complementary pairs of bit lines. The CAM cell further includes a pair of comparison circuits, each for comparing said data value stored in said SRAM cell with a search data value provided on a corresponding search line. A CAM cell has an equal number of n-channel and p-channel devices. CAM cells use P-channel transistors as access transistors to SRAM cells to improve the layout efficiency of the cell array. This implementation ensures a balanced number of p-channel and n-channel devices per cell while still providing excellent functional characteristics.