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Content-addressed memory unit

A content addressing, half-cell technology, applied in static memory, digital memory information, information storage, etc., can solve problems such as occupation

Inactive Publication Date: 2002-11-27
CONVERSANT INTPROP MANAGEMENT INC
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

But as mentioned earlier, dynamic cells require regular refresh operations to maintain data, and such refresh circuits take up additional silicon area

Method used

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Embodiment Construction

[0021] refer to Figure 5 , with reference numeral 500 representing an SRAM-based CAM cell in the prior art. The CAM cell includes two 6T SRAM cells 502 . Each SRAM cell 502 includes two p-channel transistors and two n-channel transistors cross-connected in the relationship of inverters 506, and two n-channel transistors 508 for access from a pair of bit lines 510 device. The CAM cell further includes a comparator circuit 512 with four additional n-channel transistors 508 for implementing a "AND" logic function for comparing search data and stored data.

[0022] Figure 5 The main problem with this implementation, represented in , is the imbalance between transistor types, which leads to a non-optimal layout of the CAM cells. In particular, out of a total of 16 transistors, only 4 are P-channel devices. In addition, all n-channel devices in a cell need to be located in a common p-diffusion. This region includes n-channel access device 508 , n-channel cross-connected inve...

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Abstract

A three-state content addressable memory (CAM) cell comprising a pair of static random access memory (SRAM) cells each including a pair of cross-connected inverters for storing data values, and a pair of inverters for An access device for accessing complementary pairs of bit lines. The CAM cell further includes a pair of comparison circuits, each for comparing said data value stored in said SRAM cell with a search data value provided on a corresponding search line. A CAM cell has an equal number of n-channel and p-channel devices. CAM cells use P-channel transistors as access transistors to SRAM cells to improve the layout efficiency of the cell array. This implementation ensures a balanced number of p-channel and n-channel devices per cell while still providing excellent functional characteristics.

Description

technical field [0001] The present invention relates to a content-addressable memory unit, in particular to a three-state content-addressable memory (CAM) half-unit. Background technique [0002] Conventional content addressable memory (CAM) has been primarily implemented using static random access memory (SRAM) cells. Due to the high access speed of SRAM memory cells and the static nature of the cells, SRAM-based CAMs are widely used. Furthermore, SRAM cells can be fabricated using a logic-only manufacturing process commonly used for non-memory circuit blocks. [0003] In addition to the random access memory (RAM) function of writing and storing data, the CAM also searches and compares the stored data to determine if the data matches the search data applied to the memory. When the newly added search data matches the data already stored in the memory, a match result is indicated, and if the search data does not match the stored data, a mismatch result is indicated. CAM is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C15/00G11C15/04H10B10/00
CPCG11C15/04G11C15/00
Inventor 理查德·福斯
Owner CONVERSANT INTPROP MANAGEMENT INC
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