A crossed iron electric memory array structure

Abstract

The invention discloses an X-shaped ferroelectric memory array structure which belongs to the integrated circuit design manufacturing technical field. The array structure of the invention takes X-shaped ferroelectric memory cells as basic components, wherein, each ferroelectric memory cell respectively shares a control line CL with memory cells in the same row or the same column in the horizontal-vertical direction; the memory cells in the same column shares a data signal line BL in the column direction; the memory cells in the same row shares a BL in the row direction; rows and columns do notshare BLs. The X-shaped ferroelectric memory array structure is based on a data storage and read-write mechanism of a ferroelectric memory and borrows ideas from partial principles and read-write means of an FeRAM incorporated PL array architecture, thereby control and data read-write of the memory cells can be simultaneously performed along the row direction and the column direction and parallelread-write of multi-bit data can be easily realized; the symmetry of circuits and the arrangement of peripheral circuits are optimized; the number and the scale of decoding and drive circuits are reduced; moreover, the length of the BL line can be reduced and then the read-write speed is improved.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, in particular to a cross-type ferroelectric memory array structure. Background technique [0002] Ferroelectric memory is a new type of memory device manufactured using the hysteresis characteristics of ferroelectric capacitance. Mainstream ferroelectric memories (FeRAM) are mostly arrays based on 1T1C cells or 2T2C cells. In such arrays, although the number of data bits is different, each memory array includes three kinds of signal lines, namely PL (plate signal line), WL (gate signal line) and BL (data signal line). In this array structure, the memory cells are arranged in regular rectangles, WL and PL are mutually independent signals, and WL / PL are not multiplexed between different rows (or different columns). Image 6 and Figure 7 They are 1T1C array structure and 2T2C array structure respectively. It can be seen that under such a structure, the capacity of the storage array can b...

AI Technical Summary

Problems solved by technology

As a result, such difficulties are caused: under the same capacity, on the one hand, reducing the number of bits of WL / PL will increase the number of data bits, so that it is necessary to increase signal pins or add signal gating circuits and two-dimensional decoding. Increase the complexity and area of ​​the circuit; on the other hand, ensuring a certain number of signal pins may increase the number of WL / PL bits and extend the length of the signal line, which is not conducive to the scale of the decoder and the operation speed

Different WL and PL placement methods cannot effectively optimize the storage array, so a new storage array structure with fundamentally different control methods is needed to achieve a more optimized memory design

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