67results about How to "Improve forward conduction characteristics" patented technology

The invention discloses a silicon carbide TrenchMOS device and manufacturing method thereof, belonging to the technical field of power semiconductors. Considering the defects of an external anti-parallel fast recovery diode (FRD) and a parasitic diode directly using a silicon carbide TrenchMOS device, a polysilicon area is additionally arranged in the p+ contact area of a conventional device, so that a Si/SiC heterojunction is formed by the polysilicon and silicon carbide epitaxial layer material, and furthermore, a diode is integrated in the device. The junction voltage drop is significantly reduced when a device diode is applied, and the conductive mode during the diode application is converted from bipolar conduction into single polar conduction, so that the silicon carbide TrenchMOS device has the advantages of short reverse recovery time and less reverse recovery charge. The device structure also has the advantages of low parasitic silicon carbide diode reverse leakage, high breakdown voltage and good device temperature stability. Therefore, the silicon carbide TrenchMOS device has wide prospects in circuits such as an inversion circuit and a chopper circuit.

The invention discloses a trenched Schottky-barrier diode, and solves the problems that a conventional trenched Schottky-barrier diode is lower in performance and reliability, high in reverse current leakage and poor in reverse blocking capability. The doping density of an epilayer gradually increases from the top to bottom, a second conduction type non-uniformly doped conductive polycrystalline silicon of which the doping density gradually decreases from the top to bottom is filled in trenches, second conduction type heavily doped lug boss apex angle protection areas are formed at the apex angles on two sides of lug bosses, and a Schottky-barrier metal layer in ohmic contact with the top surfaces of both the conductive polycrystalline silicon and the lug boss apex angle protection areas is added to the bottom surface of an anodal metal layer. The trenched Schottky-barrier diode provided by the invention has the advantages of low reverse current leakage, good voltage reverse blocking capability and excellent reliability. The invention also provides a manufacturing method of the trenched Schottky-barrier diode, which has the advantages of less steps and low manufacturing cost and can effectively isolate areas from damage by the technological process and contamination of impurities due to local impairment of isolating layers.

The invention belongs to the technical field of power semiconductor devices, and relates to a RET IGBT with a self-biased PMOS and a manufacturing method thereof. According to the RET IGBT with the self-biased PMOS and the manufacturing method thereof, a N-type charge storage layer is arranged between a P-type base region and a P-type buried layer, so that the influence of the N-type charge storage layer on the breakdown voltage of the device can be shielded while the forward conduction characteristic of the device is improved; by introducing a PMOS structure, an extra path is provided for theextraction of holes, the extraction speed of current carriers is accelerated, the switching speed of the device is improved, and the turn-off loss of the device is reduced; and meanwhile, an emitterembedded type separation gate structure can meet the requirement that a table top of the device is further narrowed to improve the forward conduction characteristic of the device, metal and contact holes of the emitter of the device can be easily and irregularly made, and meanwhile, the Miller capacitance of the device can be reduced further.

The invention discloses a groove schottky semiconductor device with a super junction structure. Charge compensation can be formed by second conductive semiconductor materials located on the lower portions inside grooves and first conductive semiconductor materials among the grooves, then the super junction structure is formed, and reverse breakdown voltages of devices are improved; meanwhile, when a semiconductor device is connected with a certain reverse bias voltage, a metal oxide semiconductor (MOS) structure is constructed by the second conductive semiconductor materials which are doped with metal or high-concentration impurities and arranged on the upper portions inside the grooves and insulating medium located on the side surfaces of the grooves, electric field intensity of drifting materials nearby schottky barrier can be restrained, the pheromone that the barrier height of the schottky barrier is reduced along with rising of the reverse bias voltage is reduced, accordingly reverse leakage current of the devices is reduced, and a reverse blocking characteristic of the devices is improved.

The invention relates to an SOI (Silicon on Insulator) substrate folding grid insulating tunneling enhanced transistor. The transistor is provided with insulating tunneling structures on the two sides and the upper surface of a base region simultaneously, so the insulating tunneling effect occurs on the two sides and the upper surface of the base region simultaneously under the control effect of a grid electrode, and thus the generation rate of tunneling current is improved; compared with MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) or TFETs (Tunneling Field-Effect Transistor) devices of the same size, superior switching characteristic is realized by using the extremely sensitive mutual relation between the impedance of a tunneling insulating layer and the field intensity in the tunneling insulating layer; superior forward turn-on characteristic is realized by enhancing a tunneling signal through an emitter electrode; besides, the invention also provides specific manufacturing methods of an SOI substrate folding grid insulating tunneling enhanced transistor unit and an array of the enhanced transistor unit. According to the transistor, the working characteristic of a nanoscale integrated circuit unit is obviously improved; the transistor is suitable for popularization and application.

The invention relates to a high performance SOI non-junction transistor of a non-monolithic substrate insulation layer thickness. An employed SOI wafer insulation layer thickness is not single-valued in the unit length of a transistor. By properly increasing the thickness of the parts, near a source region and a drain region, of an SOI wafer insulation layer, the resistance of the source region and the drain region is greatly reduced, and the positive onset property of a component is greatly improved. By properly decreasing the thickness of the parts, under corresponding gate electrodes, of the SOI wafer insulation layer, local enhancement on the voltage regulating effect of a substrate can be achieved, the substrate voltage bias needed for auxiliary grid control can be lowered, and voltage control over the lower part of the substrate can be achieved. By optimizing the relative positions and sizes of the thicker part and the thinner part of the insulation layer of the SOI wafer, the reverse leakage current caused by band-to-band tunneling around the junctions of a component channel and drain electrodes when reversal of biasing of the gate electrodes occurs is effectively reduced. Therefore, the high performance SOI non-junction transistor is suitable for widespread application.

The invention discloses a groove charge compensation Schottky semiconductor device which is provided with a charge compensation structure. When the semiconductor device is connected with certain back bias voltage, a first conducting semiconductor material and a second conducting semiconductor material can form charge compensation and the back blocking property of a device is improved. A polycrystal semiconductor material is led into the upper portion of the groove so that strength of a peak electric field of Schottky junction surface can be reduced when the semiconductor device is connected with the back bias voltage and the back blocking property of the device is further improved. The invention further provides a manufacturing method of the groove charge compensation Schottky semiconductor device.

The invention discloses a high-barrier SiC JBS device and a preparation method thereof. The device comprises a first electrode layer, a SiC substrate, an N-SiC epitaxial layer, a second electrode layer, a dielectric layer and a PI layer which are arranged from top to bottom. According to the SiC device, a JBS structure and a surface low-concentration structure are formed on the epitaxial layer, sothat the barrier height of the device is increased, and meanwhile, the electric leakage characteristic of the device is reduced.

The invention discloses a Schottky semiconductor device with an insulating layer isolated super-junction structure. By a groove structure, a deeper strip-shaped P-type semiconductor silicon material can be realized, when the device is connected with reverse bias, the strip-shaped P-type semiconductor silicon material and an N-type semiconductor silicon material form charge complementation to form the super-junction structure, and the electric field intensity distribution of a drift region is changed to form a flat electric field intensity distribution curve. The invention also provides a preparation method for the Schottky semiconductor device with the insulating layer isolated super-junction structure.

The invention discloses a Schottky semiconductor device with grooves. The Schottky semiconductor device with the grooves comprises an MOS structure, a PN junction and a Schottky barrier junction. The electric field distribution of reverse bias voltage is changed through the MOS structure, and therefore the forward-direction conductive character of a component is improved. The bearing capacity of transient high voltage of the component is improved through the PN junction. When the semiconductor device is under the forward-direction small electric current density state, the PN junction is not opened, and therefore minority carrier injection of the component is reduced, and the reverse recovery character of the component is improved. The invention provides a preparation method of the Schottky semiconductor device with the grooves.

The invention relates to an insulated gate tunneling bipolar transistor with a U-shaped tunneling insulating layer. A gate electrode tunneling current is generated by the U-shaped tunneling insulating layer, and the very sensitive mutual relation between impedance of the tunneling insulating layer and intensity of an internal electric field of the tunneling insulating layer is utilized to enable the U-shaped tunneling insulating layer to implement conversion between a high impedance state and a low impedance state in a very short electric potential change interval of a gate electrode, and thus, compared with the prior art, the insulated gate tunneling bipolar transistor can realize a better switching characteristic; by bipolar amplification, the positive conduction characteristic of a nanoscale insulated gate transistor is obviously improved. The invention also discloses a specific manufacturing method of the insulated gate tunneling bipolar transistor with the U-shaped tunneling insulating layer. Therefore, the working characteristic of a nanoscale integrated circuit unit is obviously improved, and the insulated gate tunneling bipolar transistor and the manufacturing method are suitable for being popularized and applied.

The invention belongs to the technical field of power semiconductor devices, and relates to a separation gate SiCMOSFET of an integrated heterojunction diode and a manufacturing method of the separation gate SiCMOSFET. According to the invention, the heterojunction diode is integrated in the three-dimensional y direction of the SiC MOSFET, so that the cell width of the SiC MOSFET is not increased, the problems of overlarge forward turn-on voltage drop, overlong reverse recovery time and the like of a parasitic diode can be effectively solved, and compared with an internally integrated SBD, the integrated heterojunction diode has smaller forward voltage drop. According to the mode of integrating the heterojunction diode, the area of an active region does not need to be additionally increased, the integration level is higher, and the width of the JFET region is not increased. Meanwhile, the spaced P-type doped regions are introduced in the y direction of the JFET region, so that the electric field distribution of the JFET region of the device and the peak electric field in the oxide layer during blocking work can be improved, a CSL layer with higher concentration can be adopted during design, and the forward conduction characteristic of the device is improved and the resistance of the device during forward conduction is reduced while the reverse blocking characteristic of the device is not reduced.

The invention discloses a groove schottky semiconductor device which is provided with a charge compensation structure. First conducting semiconductor materials and second conducting semiconductor materials can form charge compensation when the semiconductor device is connected with a certain reverse bias, so that positive conducting or reverse blocking characteristics of the device can be improved. The invention further provides a manufacturing method of the groove schottky semiconductor device.

The invention relates to a hybrid Schottky barrier diode structure with a P-type nickel oxide material. The structure comprises a bottom ohmic contact electrode, an N+ substrate, an N-drift layer, a groove, a P-type layer, a field plate dielectric layer, field plate metal and a Schottky contact electrode, the N-drift layer is of a step structure, and p-NiO materials are grown on selected areas on the two sides of a table top to replace P-type wide bandgap semiconductor materials. Therefore, the problem that a P-type epitaxial growth technology and an ion implantation technology of a wide bandgap semiconductor material at the present stage are immature can be well solved. The structure is high in operability, low in cost, simple and reliable in process and suitable for industrial application and popularization.

The invention discloses a Schottky semiconductor device with a charge compensation groove. According to the Schottky semiconductor device with the charge compensation groove, a charge compensation structure can be formed by a first conductive semiconductor material and a second conductive semiconductor material, electric field intensity which can reduce Schottky junctions on the surface of the first conductive semiconductor material exists in the groove in the surface of the device, and then reverse breakdown voltage of the device is improved. The invention further provides a preparing method of the Schottky semiconductor device with the charge compensation groove.

The invention discloses a schottky semiconductor device which is provided with a charge compensation structure. When the semiconductor device is connected to a certain reverse bias voltage, first electric conduction semiconductor material and second electric conduction semiconductor material can form charge compensation, and the characteristic of forward conduction or reverse blocking of the device is improved. The invention further provides a method for preparing the schottky semiconductor device.