50results about How to "Increase the forward conduction current" patented technology

The invention discloses a one-way conductive pressure device with characteristics including: an N well is formed at a left side of an upper part of a P-type silicon and N+ injection layers are formed above the N well; more than two serially connected MOS structures including the P-type silicon, the N+ injection layers, gate oxide layers and gates are formed at a right side of the upper part of the P-type silicon; the gate oxide layers are formed on the P-type silicon; the N+ injection layers are formed at an upper part of the P-type silicon and beneath two sides of the gate oxide layers; and the gates are arranged on the gate oxide layers, wherein a gate oxide layer of a leftmost MOS structure is adjacent to the N well, and the gate of each MOS structure is connected with adjacent N+ injection layers through mental wires. The invention also discloses a manufacturing method for the one-way conductive pressure device The invention also discloses a manufacturing method for the one-way conductive pressure device Compared with traditional high-voltage diodes, the one-way conductive pressure device is capable of providing higher forward-direction conduction current while providing the same breakdown-resistant voltage.

The invention relates to a highly integrated grooved insulating gate tunneling bipolar enhancement transistor. Compared with MOSFETs or TFETs devices of the same size, the extremely sensitive relationship between the impedance of the tunneling insulating layer and its internal field strength is used to realize excellent switching characteristics; Extremely enhances the tunneling signal to achieve excellent forward conduction characteristics; compared with the ordinary planar structure, it avoids the sequential arrangement of the emitter region 3, the base region 4 and the collector region 5 along the horizontal direction, thus saving the chip area and realizing more High level of integration. In addition, the invention also proposes a specific manufacturing method of a highly integrated recessed insulated gate tunneling bipolar enhancement transistor. The transistor significantly improves the working characteristics of the nanoscale integrated circuit unit and is suitable for popularization and application.

An epitaxial structure of a silicon carbide device and a preparation method thereof relate to the technical field of semiconductor devices. The method includes: growing a silicon carbide epitaxial layer on a substrate; depositing a first barrier layer on the silicon carbide epitaxial layer; etching the first barrier layer to form a first window exposing the silicon carbide epitaxial layer, and injecting N through the first window type ions to form an N-type ion implantation region in the silicon carbide epitaxial layer; a continuous second barrier layer is grown on the first barrier layer and in the first window, and the second barrier layer encloses the first window to form a second window ; Etch the second barrier layer to expose the N-type ion implantation region at the second window, and retain the second barrier layer at the sidewall of the first window to form a sidewall structure; In the N-type ion implantation region by ion implantation A P-type ion implantation region is formed, and the implantation depth of the P-type ion implantation region in the silicon carbide epitaxial layer is greater than the implantation depth of the N-type ion implantation region in the silicon carbide epitaxial layer.

The invention discloses a parasitic N-I-P type PIN device structure in a BiCMOS (bipolar complementary metal oxide semiconductor) process. The parasitic N-I-P type PIN device structure is characterized in that an active area is formed above a P type substrate, a P type embedded layer is formed in the active area, a plurality of shallow trench isolators are formed above the P type embedded layer, polycrystalline silicon layers are formed above the shallow trench isolators, emitting areas are formed above the active area, the emitting areas and the polycrystalline silicon layers are alternately arranged, the emitting areas are connected with metal wires in a leading-out manner through contact holes, the P type embedded layer is connected with a metal wire in a leading-out manner through a deep contact hole, and titanium or tin and tungsten are arranged in the deep contact hole. The invention further discloses a manufacturing method of the parasitic N-I-P type PIN device structure in the BiCMOS process. By the aid of the parasitic N-I-P type PIN device structure and the manufacturing method thereof, forward breakover current and the effective area of a PIN device can be increased, and insertion loss of the PIN device is reduced.

The present invention discloses a gallium nitride diode and a manufacturing method thereof. The gallium nitride diode comprises a substrate; a first channel layer disposed above the substratel a first barrier layer disposed on the first channel layer, a first two-dimensional electron gas being formed between the first barrier layer and the first channel layer; a cap layer structure disposed on the first barrier layer; a cathode disposed on the first barrier layer at one side of the cap layer structure and / or extending into the first barrier layer, a gap being arranged between the cap layer structure and the cathode; and anodes disposed at the first barrier layer at the other side of the cap layer structure and / or extending into the first barrier layer, the anodes covering to an upper surface of the cap layer structure. The gallium nitride diode provided by the present invention has characteristics of being low in threshold voltage and on resistance, high in positive breakover current and negative withstanding voltage, and low in negative electric leakage.

The invention relates to a source-drain resistive random bidirectional switching field effect transistor and a manufacturing method thereof. The device has the structural characteristic of bilateral symmetry, and a metal source-drain interchangeable region is controlled to act as a source region or a drain region by adjusting the source-drain interchangeable electrode voltage so as to change the direction of schottky barrier tunneling current. The device has the advantages of low static power consumption reverse leakage current and low sub-threshold swing and can realize the bidirectional switching function. Compared with the common MOSFETs type device, the intensity of the schottky barrier tunneling effect is controlled by using the gate electrode to change the resistance value of the source region and the drain region so as to realize the better switching characteristic; compared with the tunneling field effect transistor, the bidirectional switching field effect transistor has the source-drain interchangeable bidirectional symmetrical switching characteristic which is not possessed by the common tunneling field effect transistor and higher forward conduction characteristic; andcompared with the common schottky barrier transistor, the bidirectional switching field effect transistor has the advantages of high technology implementation and better reverse switching characteristic so as to be suitable for popularization and application.

The invention discloses a PIN device in a bipolar complementary metal oxide semiconductor (BiCMOS) process. The PIN device is formed on a P-type silicon substrate; an active region is isolated through a shallow slot field oxide; and on an overlook surface, the layout structure of the PIN device is octagonal, polygonal over octagonal or round. On a cross section, the PIN device comprises an N-type region, an I-type region and a P-type region, wherein the N-type region consists of a shallow slot field oxide bottom of two sides of the active region and an N-type embedded layer in a transverse distance away from the active region and is led out through deep hole contact; the I-type region consists of an N-type collector implantation region formed in the active region; and the P-type region consists of an intrinsic base region epitaxial layer which is formed on the surface of the active region and doped with P-type impurities. The series resistance of the device can be effectively reduced, the forward conduction current of the device is improved, the current of the device is more uniform in each direction, and the properties of the device are improved.