High performance SOI non-junction transistor of non-monolithic substrate insulation layer thickness

Abstract

The invention relates to a high performance SOI non-junction transistor of a non-monolithic substrate insulation layer thickness. An employed SOI wafer insulation layer thickness is not single-valued in the unit length of a transistor. By properly increasing the thickness of the parts, near a source region and a drain region, of an SOI wafer insulation layer, the resistance of the source region and the drain region is greatly reduced, and the positive onset property of a component is greatly improved. By properly decreasing the thickness of the parts, under corresponding gate electrodes, of the SOI wafer insulation layer, local enhancement on the voltage regulating effect of a substrate can be achieved, the substrate voltage bias needed for auxiliary grid control can be lowered, and voltage control over the lower part of the substrate can be achieved. By optimizing the relative positions and sizes of the thicker part and the thinner part of the insulation layer of the SOI wafer, the reverse leakage current caused by band-to-band tunneling around the junctions of a component channel and drain electrodes when reversal of biasing of the gate electrodes occurs is effectively reduced. Therefore, the high performance SOI non-junction transistor is suitable for widespread application.

Description

Technical field: [0001] The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and relates to a specific structure, a structural unit and a manufacturing method of an array of high-performance SOI non-junction transistors with non-single substrate insulating layer thickness suitable for ultra-high-integration integrated circuit manufacturing. Background technique [0002] With the increasing integration of integrated circuits, the size of unit devices in the circuit continues to shrink. For the traditional integrated circuit unit, that is, the traditional metal oxide semiconductor field effect transistor (MOSFET), when the size reaches the nanometer level, on the one hand, the short channel effect has a significant impact on the device characteristics; on the other hand, in a few nanometers The manufacture of PN junctions under the scale has extremely high requirements for high technology. Compared with the traditional MOSFET, the multi-ga...

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Problems solved by technology

However, since the insulating layer between the substrate electrode and the single crystal silicon film is an insulating layer with a uniform thickness, the substrate voltage controls the carrier distribution in the single crystal silicon film below the gate electrode, It will also seriously affect the carrier distribution near the source and drain regions.

Taking the N-type junction-free transistor as an example, the reverse-biased substrate voltage increases significantly while the auxiliary gate electrode empties the electrons in the single crystal silicon film under the gate electrode to form a good blocking characteristic of the device. The resistance of the source and drain regions will seriously affect the forward conduction characteristics of the device

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