A method and apparatus for transferring wide data (e.g., n bits) from a narrow
bus (m bits, where m<n) for updating a wide data storage array. The apparatus includes: a staging latch accommodating m bits, e.g., 32 bits; control circuitry for depositing the m bits of data from a data
bus port into the staging latch addressed using a specific register address; and control circuitry adapted to merging the m bit data contained in the staging latch with m bit data from a data
bus port, to generate the n bit wide data, for example, 64 bits, that is written atomically to a storage array specified by an address corresponding to a storage array location. Thus, writing a first set of bits to the staging latch is performed by providing, as a target address of a write (store) operation, the mapped address of the staging latch, and then providing a subsequent set of bits (the remaining bits) together with an
array element target specification (encoded as a plurality of the bits of the address specified in the write transaction), in a subsequent write transaction (store).