33results about How to "Control profile" patented technology

The invention relates to a groove-forming method in a laminated medium layer, which comprises: a first medium layer is formed on a semiconductor base; a first opening is formed on the first medium layer; a first sacrificial layer is filled in the first opening; at least a second medium layer is formed on the first medium layer, and a second opening is formed on the second medium layer; the second opening is positioned above the first opening, and the depth of the second opening is same with the thickness of the second medium layer; the second sacrificial layer is filled in the second opening; the first sacrificial layer and the second sacrificial layer are removed. The invention has an advantage of capability of forming a better groove contour.

Composition comprising one or more energy donors and one or more energy acceptors, wherein energy is transferred from the energy donor to the energy acceptor and wherein: the energy acceptor is a colloidal nanocrystal having a lower band gap energy than the energy donor; the energy donor and the energy acceptor are separated by a distance of 40 nm or less; wherein the average peak absorption energy of the acceptor is at least 20 meV greater than the average peak emission energy of the energy donor; and wherein the ratio of the number of energy donors to the number of energy acceptors is from about 2:1 to about 1000:1.

The invention discloses a drivage peripheral hole homoenergetic blasting method. Peripheral holes (6) are dug on a roadway contour line of a surrounding rock (1) at the end part of a roadway; explosives (4) and cushioning materials (3) are alternatively arranged in each peripheral hole (6) from inside to outside; the explosives (4) in the adjacent peripheral holes (6) are distributed in a shape of a Chinese character pin; detonators (5) are arranged in sections along the explosives (4); nonel tubes (9) of the detonators (5) are led out of the holes along the hole walls of the peripheral holes (6); hole orifices of the peripheral holes (6) are plugged by stemming (2); then detonation is carried out according to a designed detonation network connecting line. According to the method disclosed by the invention, the explosives (4) and the cushioning materials (3) are distributed symmetrically, so that energy is more uniformly distributed, an energy utilization rate of the explosives is improved, a contour of a roadway section is well controlled, the back break phenomenon is avoided, and roadway supporting cost is reduced; meanwhile, the uniformly distributed explosive energy can enable a fragment size for blasting to be uniform, obviously improve a blasting effect and improve shovel-loading efficiency after blasting.

The invention discloses a semiconductor device and a manufacturing method thereof and an electronic device. The method comprises the following steps: forming a first hard mask layer, a second hard mask layer, a sacrificial layer and a third hard mask layer on a semiconductor substrate in sequence; carrying out etching process to form shallow trenches; filling isolation material layers in the shallow trenches; carrying out back etching to remove the sacrificial layer; removing the second hard mask layer; removing the first hard mask layer; forming a tunneling oxide layer on the exposed semiconductor substrate; forming a floating gate material layer on the semiconductor substrate; and carrying out planarization process. The manufacturing method provides a good process window for the formation of a shallow trench isolation structure oxide layer and floating gate polycrystalline silicon; contour of a floating gate is controlled well; and the physical contour of the floating gate helps to improve coupling efficiency of the device.

The invention belongs to the technical field of target extraction, particularly relates to a color-based writing trace extraction method, system and device under a complex background, and aims to solve the problems that an existing extraction method is incomplete in writing trace extraction and high in image quality requirement, and writing traces with changed colors cannot be extracted under a complex environment. The method comprises the steps of converting a to-be-detected image containing a to-be-detected writing trace into an HSV color space, selecting seed points based on the HSV color space, and dynamically obtaining pixel points on an edge image from the seed points to serve as newly-added to-be-traversed points; and based on the seed points and newly added points to be traversed,obtaining a pixel set of writing traces to be detected through image refinement. According to the method, the connectivity of the correction trace can be enhanced, and the correction trace can be effectively extracted in a complex scene; meanwhile, the conditions of newly-added points to be traversed are strictly set, the outline of the writing trace can be effectively controlled, excessive noiseis prevented from being introduced, and subsequent processing is facilitated.

A technique to make silicon oxide regions from porous silicon and related semiconductor structures are disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.

A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.

The invention discloses a method for preparing a vertically stacked SiNWFET based on bulk silicon, comprising: providing an integrated silicon substrate, on which SiGe layers and Si layers are alternately grown; Photolithography and etching to form a fin-shaped active region, and the remaining SiGe layer and Si layer are used as source and drain regions; the SiGe layer in the fin-shaped active region is removed by selective etching to form silicon nanowires, the Silicon nanowires are stacked vertically; a gate oxide layer is formed on the silicon nanowires, bulk silicon substrate, and source and drain regions; a gate is formed on the bulk silicon substrate between the source and drain regions; An isolation dielectric layer is formed between the drain region and the gate. The invention is based on bulk silicon and has no self-heating effect; adopts a conventional gate oxide layer; and is a rear isolation layer process without side wall process; the active area and the upper surface of the gate are on the same horizontal plane, which is beneficial to the subsequent contact hole process. The silicon nanowires are vertically stacked, which is beneficial to increase the integration degree of the device and the current driving capability of the device.

The invention discloses a method for welding a bushing on a flat tube, comprising: 1. Inserting a skid into the flat tube; 2. Fitting and welding the middle section of the U-shaped bushing to one surface of the flat tube; 3. 1. Bend the two cantilevers of the bushing to fit the other side of the flat tube. 4. Place a high-conductivity metal sheet on the outside of the bushing on the welded surface, and connect the metal sheet to the flat tube with a metal wire ; Five, the unwelded surface of the welded flat tube. With this method, the surface of the conduit can be controlled to ensure that the conduit is not deformed during the welding process; the distribution position of the solder joints can be freely selected to ensure the accuracy of the number and position of the solder joints.

Composition comprising one or more energy donors and one or more energy acceptors, wherein energy is transferred from the energy donor to the energy acceptor and wherein: the energy acceptor is a colloidal nanocrystal having a lower band gap energy than the energy donor; the energy donor and the energy acceptor are separated by a distance of 40 nm or less; wherein the average peak absorption energy of the acceptor is at least 20 meV greater than the average peak emission energy of the energy donor; and wherein the ratio of the number of energy donors to the number of energy acceptors is from about 2:1 to about 1000:1.

A method for fabricating a MOSFET is provided. The method comprises: providing a substrate, the substrate having a gate structure; forming a drain region and a source region in the substrate, the drain region and the source region being on two sides of the gate structure respectively; forming a metal suicide layer on the surface of the gate structure, the drain region, and the source region; forming a patterned block on the metal silicide layer above the gate structure, and forming a first dielectric layer above the substrate except the gate strcutre, the patterned block being formed above the center of the gate structure and the metal silicide layer above the gate structure beside two sides of the patterned block being exposed; removing a portion of the metal silicide layer and a portion of the gate structure by using the patterned block as a mask; and forming a drain extension region and a source extension region in the substrate, beside two sides of the remaining gate structure.

The invention relates to an embedded flash memory, a preparation method thereof, and an electronic device. The method comprises that a substrate is provided, an active region isolated by a shallow trench isolation (STI) oxide is formed in the substrate, and the top of the STI oxide is higher than the surface of the substrate; a floating gate material layer is deposited to cover the active region and the STI oxide; the floating gate material layer is flattened to expose the surface of the STI oxide; the floating gate material layer is etched back to reduce the thickness of the floating gate material layer and expose the STI oxide of certain height; the exposed STI oxide is etched back to reduce the key size of the exposed STI oxide; the floating gate material layer is re-deposited till the top of the STI oxide to surround the STI oxide and flatten the floating material layer; and the part whose key size is reduced of the STI oxide is removed to form a T-shaped floating gate on the active region.

The invention discloses a semiconductor device and a manufacturing method thereof and an electronic device. The method comprises the following steps: forming a first hard mask layer, a second hard mask layer, a sacrificial layer and a third hard mask layer on a semiconductor substrate in sequence; carrying out etching process to form shallow trenches; filling isolation material layers in the shallow trenches; carrying out back etching to remove the sacrificial layer; removing the second hard mask layer; removing the first hard mask layer; forming a tunneling oxide layer on the exposed semiconductor substrate; forming a floating gate material layer on the semiconductor substrate; and carrying out planarization process. The manufacturing method provides a good process window for the formation of a shallow trench isolation structure oxide layer and floating gate polycrystalline silicon; contour of a floating gate is controlled well; and the physical contour of the floating gate helps to improve coupling efficiency of the device.

The invention relates to a horizontal well automatic water control valve. The horizontal well automatic water control valve mainly comprises a valve base 1 and a valve cover 6; the valve base 1 comprises a unit I, a unit II, a unit III and a unit IV which are the same, and the four units are provided with flow guide grooves with the same structure correspondingly; and the flow guide grooves conduct water control by utilizing the following principles that (1) a density difference exists between oil and water, and an oil-water mixed phase can be separated when rotating; and (2) streamwise friction can be generated when fluid flows in the flow guide grooves. The unit I in the valve base 1 is taken as an example to conduct specific explaining: when flowing into a first-stage flow guide groove 3 through an inlet 2, the oil-water mixed phase can be separated into oil and water single phases through rotating, wherein the oil phase flows out directly along an outlet 5, the water phase can continue to flow for a certain distance along a second-stage flow guide groove 4 and then flows out along the outlet 5, thus the streamwise friction of the water phase is increased, and therefore the purpose of controlling water is achieved. The horizontal well automatic water control valve has the beneficial effects that the horizontal well automatic water control valve has no movable component, and is suitable for a sand producer; and, meanwhile, filtrational resistance of a producing area with the high water content can be increased, and the purposes of balancing a fluid producing profile and enhancing the recovery efficiency are achieved.

The invention discloses a semiconductor device and a manufacturing method thereof and an electronic device. The method comprises the following steps: forming a hard mask layer on a semiconductor substrate; etching the hard mask layer and the semiconductor substrate; filling isolation material layers in shallow trenches respectively; removing the hard mask layer to expose the semiconductor substrate; forming a tunneling oxide layer on the exposed semiconductor substrate; forming a first floating gate material layer on the semiconductor substrate; forming a sacrificial layer on the semiconductor substrate; removing the first floating gate material layer uncovered with the sacrificial layer; removing the sacrificial layer; and forming a second floating gate material layer on the first floating gate material layer by adopting an epitaxial growth process. The manufacturing method provides a good process window for the formation of a shallow trench isolation structure oxide layer and floating gate polycrystalline silicon; contour of a floating gate is controlled well; and the physical contour of the floating gate helps to improve coupling efficiency of the device.

The invention relates to the technical field of semiconductor manufacturing process polishing, in particular to a carrier head and a polishing device having the same. The carrier head includes: a body made of non-flexible material, the end of the body close to the wafer to be polished is provided with a plurality of concave cavities, and each concave cavity is provided with a ventilation hole connected with the air source; the flexible film is fixedly connected to the end, suitable for in contact with the wafer to be polished. By setting the body to be made of inflexible material, it is convenient to open a plurality of concave cavities on the body, and a ventilation hole connected to the air source is arranged on the concave cavity, so that the air pressure control of each concave cavity is more convenient. The end of the polished wafer is fixedly connected to the flexible film, and the flexible film is used to contact the wafer to be polished to ensure the fit between the flexible film and the wafer to be polished. The non-flexible material body is used to directly open a concave cavity in the form of a flexible film to ensure the independent control of each cavity, so that the structure and process of the bearing head are relatively simple.

The invention discloses a drivage peripheral hole homoenergetic blasting method. Peripheral holes (6) are dug on a roadway contour line of a surrounding rock (1) at the end part of a roadway; explosives (4) and cushioning materials (3) are alternatively arranged in each peripheral hole (6) from inside to outside; the explosives (4) in the adjacent peripheral holes (6) are distributed in a shape of a Chinese character pin; detonators (5) are arranged in sections along the explosives (4); nonel tubes (9) of the detonators (5) are led out of the holes along the hole walls of the peripheral holes (6); hole orifices of the peripheral holes (6) are plugged by stemming (2); then detonation is carried out according to a designed detonation network connecting line. According to the method disclosed by the invention, the explosives (4) and the cushioning materials (3) are distributed symmetrically, so that energy is more uniformly distributed, an energy utilization rate of the explosives is improved, a contour of a roadway section is well controlled, the back break phenomenon is avoided, and roadway supporting cost is reduced; meanwhile, the uniformly distributed explosive energy can enable a fragment size for blasting to be uniform, obviously improve a blasting effect and improve shovel-loading efficiency after blasting.

The invention discloses a semiconductor device and a manufacturing method thereof, and an electronic device. The method comprises the following steps: forming a hard mask layer on a semiconductor substrate; etching the hard mask layer and the semiconductor substrate so as to form a shallow trench; filling an isolation material layer in the shallow trench; removing the hard mask layer; forming a tunneling oxide layer on the exposed semiconductor substrate; forming a first floating gate material layer on the semiconductor substrate; executing a planarization technology; forming a second floating gate material layer whose width is greater than that of the first floating gate material layer on the first floating gate material layer by use of an epitaxial growth technology; and successively forming a dielectric layer and a control gate material layer on the semiconductor substrate. According to the manufacturing method provided by the invention, a good technical window is provided for forming a shallow trench isolation structure oxide layer and floating gate polysilicon.

The embodiment of the present application discloses a method for forming a monitoring reference mark, a monitoring reference mark, and a three-dimensional memory, wherein the method is applied to the formation process of a three-dimensional memory, including: providing a semi-finished semiconductor, the semiconductor including a substrate and a deposition A stacked structure on the substrate; through the formation process of the top selection gate trench of the three-dimensional memory, a monitoring reference mark is formed at a specific position on the top of the stacked structure; wherein, the monitoring reference mark Embedded in the top of the stacked structure; through the formation process of the ladder structure of the three-dimensional memory, the top of the stacked structure including the monitoring reference mark is etched, so that the monitoring reference mark is on the The top of the laminated structure protrudes.

The invention relates to a manufacturing method of a semiconductor element, which comprises the following steps of: firstly, forming a lower electrode material layer containing aluminum and copper on a substrate; secondly, forming an insulating material layer and an upper electrode material layer on the surface of the lower electrode material layer in sequence; thirdly, forming a patterned photoresist layer on the upper electrode material layer, and patterning the upper electrode material layer by using the photoresist layer as a mask to form a patterned upper electrode material layer; fourthly, ashing and removing the patterned photoresist layer by using a plasma, and fusing the patterned lower electrode material layer; and finally, patterning the insulating material layer and the lower electrode material layer to form a patterned insulating layer and a lower patterned electrode layer.