33results about How to "Control profile" patented technology

A technique to make silicon oxide regions from porous silicon and related semiconductor structures are disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.

A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.

The invention discloses a method for preparing a vertically stacked SiNWFET based on bulk silicon, comprising: providing an integrated silicon substrate, on which SiGe layers and Si layers are alternately grown; Photolithography and etching to form a fin-shaped active region, and the remaining SiGe layer and Si layer are used as source and drain regions; the SiGe layer in the fin-shaped active region is removed by selective etching to form silicon nanowires, the Silicon nanowires are stacked vertically; a gate oxide layer is formed on the silicon nanowires, bulk silicon substrate, and source and drain regions; a gate is formed on the bulk silicon substrate between the source and drain regions; An isolation dielectric layer is formed between the drain region and the gate. The invention is based on bulk silicon and has no self-heating effect; adopts a conventional gate oxide layer; and is a rear isolation layer process without side wall process; the active area and the upper surface of the gate are on the same horizontal plane, which is beneficial to the subsequent contact hole process. The silicon nanowires are vertically stacked, which is beneficial to increase the integration degree of the device and the current driving capability of the device.

Composition comprising one or more energy donors and one or more energy acceptors, wherein energy is transferred from the energy donor to the energy acceptor and wherein: the energy acceptor is a colloidal nanocrystal having a lower band gap energy than the energy donor; the energy donor and the energy acceptor are separated by a distance of 40 nm or less; wherein the average peak absorption energy of the acceptor is at least 20 meV greater than the average peak emission energy of the energy donor; and wherein the ratio of the number of energy donors to the number of energy acceptors is from about 2:1 to about 1000:1.

A method for fabricating a MOSFET is provided. The method comprises: providing a substrate, the substrate having a gate structure; forming a drain region and a source region in the substrate, the drain region and the source region being on two sides of the gate structure respectively; forming a metal suicide layer on the surface of the gate structure, the drain region, and the source region; forming a patterned block on the metal silicide layer above the gate structure, and forming a first dielectric layer above the substrate except the gate strcutre, the patterned block being formed above the center of the gate structure and the metal silicide layer above the gate structure beside two sides of the patterned block being exposed; removing a portion of the metal silicide layer and a portion of the gate structure by using the patterned block as a mask; and forming a drain extension region and a source extension region in the substrate, beside two sides of the remaining gate structure.

The invention discloses a semiconductor device and a manufacturing method thereof and an electronic device. The method comprises the following steps: forming a first hard mask layer, a second hard mask layer, a sacrificial layer and a third hard mask layer on a semiconductor substrate in sequence; carrying out etching process to form shallow trenches; filling isolation material layers in the shallow trenches; carrying out back etching to remove the sacrificial layer; removing the second hard mask layer; removing the first hard mask layer; forming a tunneling oxide layer on the exposed semiconductor substrate; forming a floating gate material layer on the semiconductor substrate; and carrying out planarization process. The manufacturing method provides a good process window for the formation of a shallow trench isolation structure oxide layer and floating gate polycrystalline silicon; contour of a floating gate is controlled well; and the physical contour of the floating gate helps to improve coupling efficiency of the device.

The invention relates to a horizontal well automatic water control valve. The horizontal well automatic water control valve mainly comprises a valve base 1 and a valve cover 6; the valve base 1 comprises a unit I, a unit II, a unit III and a unit IV which are the same, and the four units are provided with flow guide grooves with the same structure correspondingly; and the flow guide grooves conduct water control by utilizing the following principles that (1) a density difference exists between oil and water, and an oil-water mixed phase can be separated when rotating; and (2) streamwise friction can be generated when fluid flows in the flow guide grooves. The unit I in the valve base 1 is taken as an example to conduct specific explaining: when flowing into a first-stage flow guide groove 3 through an inlet 2, the oil-water mixed phase can be separated into oil and water single phases through rotating, wherein the oil phase flows out directly along an outlet 5, the water phase can continue to flow for a certain distance along a second-stage flow guide groove 4 and then flows out along the outlet 5, thus the streamwise friction of the water phase is increased, and therefore the purpose of controlling water is achieved. The horizontal well automatic water control valve has the beneficial effects that the horizontal well automatic water control valve has no movable component, and is suitable for a sand producer; and, meanwhile, filtrational resistance of a producing area with the high water content can be increased, and the purposes of balancing a fluid producing profile and enhancing the recovery efficiency are achieved.

The invention discloses a semiconductor device and a manufacturing method thereof and an electronic device. The method comprises the following steps: forming a hard mask layer on a semiconductor substrate; etching the hard mask layer and the semiconductor substrate; filling isolation material layers in shallow trenches respectively; removing the hard mask layer to expose the semiconductor substrate; forming a tunneling oxide layer on the exposed semiconductor substrate; forming a first floating gate material layer on the semiconductor substrate; forming a sacrificial layer on the semiconductor substrate; removing the first floating gate material layer uncovered with the sacrificial layer; removing the sacrificial layer; and forming a second floating gate material layer on the first floating gate material layer by adopting an epitaxial growth process. The manufacturing method provides a good process window for the formation of a shallow trench isolation structure oxide layer and floating gate polycrystalline silicon; contour of a floating gate is controlled well; and the physical contour of the floating gate helps to improve coupling efficiency of the device.

The invention relates to a manufacturing method of a semiconductor element, which comprises the following steps of: firstly, forming a lower electrode material layer containing aluminum and copper on a substrate; secondly, forming an insulating material layer and an upper electrode material layer on the surface of the lower electrode material layer in sequence; thirdly, forming a patterned photoresist layer on the upper electrode material layer, and patterning the upper electrode material layer by using the photoresist layer as a mask to form a patterned upper electrode material layer; fourthly, ashing and removing the patterned photoresist layer by using a plasma, and fusing the patterned lower electrode material layer; and finally, patterning the insulating material layer and the lower electrode material layer to form a patterned insulating layer and a lower patterned electrode layer.