Preparation method of bulk silicon-based longitudinal stack-type silicon nanowire field effect transistor (SiNWFET)

Abstract

The invention discloses a method for preparing a vertically stacked SiNWFET based on bulk silicon, comprising: providing an integrated silicon substrate, on which SiGe layers and Si layers are alternately grown; Photolithography and etching to form a fin-shaped active region, and the remaining SiGe layer and Si layer are used as source and drain regions; the SiGe layer in the fin-shaped active region is removed by selective etching to form silicon nanowires, the Silicon nanowires are stacked vertically; a gate oxide layer is formed on the silicon nanowires, bulk silicon substrate, and source and drain regions; a gate is formed on the bulk silicon substrate between the source and drain regions; An isolation dielectric layer is formed between the drain region and the gate. The invention is based on bulk silicon and has no self-heating effect; adopts a conventional gate oxide layer; and is a rear isolation layer process without side wall process; the active area and the upper surface of the gate are on the same horizontal plane, which is beneficial to the subsequent contact hole process. The silicon nanowires are vertically stacked, which is beneficial to increase the integration degree of the device and the current driving capability of the device.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for preparing a vertically stacked silicon nanowire field effect transistor (SiNWFET) based on bulk silicon. Background technique [0002] In the prior art, reducing the size of transistors to increase the working speed and integration of chips and reduce the power consumption density of chips has always been the goal pursued by the development of the microelectronics industry. In the past forty years, the development of microelectronics industry has been following Moore's law. At present, the physical gate length of field-effect transistors is close to 20nm, and the gate dielectric is only a few layers thick of oxygen atoms. It is difficult to improve the performance by reducing the size of traditional field-effect transistors, mainly because of the small size of the short channel. Channel effect and gate leakage current deteriorate the switching performance ...

AI Technical Summary

Problems solved by technology

This method can realize the vertically stacked silicon nanowire field effect transistor structure, but there is a disadvantage: when the SiGe layer is oxidized, Ge will condense to the surface of the Si layer, removing SiO 2 Finally, a layer of concentrated SiGe alloy is wrapped on the surface of silicon nanowires

Due to GeO 2 Soluble in water, it makes the follow-up process face great inconvenience, in addition, GeO 2 The dielectric constant is higher than that of SiO 2 Small, the interface state between GeO2 and Si is large, it is not suitable as the gate oxide layer of field effect transistor (FET)

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