Embedded flash memory, manufacturing method therefor, and electronic device
An electronic device and embedded technology, applied in the direction of circuits, electrical components, electric solid devices, etc., can solve the problems of holes, deposition of floating gates, etc., to avoid holes, improve coupling performance, and good breakdown voltage performance Effect
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[0055] The preparation method of the embedded flash memory described in the prior art is as Figures 1a-1g As shown, first as Figure 1a As shown, a semiconductor substrate 101 is provided on which an oxide layer 102 and a nitride layer 103 are formed and patterned to form shallow trenches in the oxide layer 102 and the nitride layer 103 , choose shallow trench oxide 104 to fill the shallow trench, and obtain the following Figure 1a pattern shown.
[0056] Then, the nitride layer 103 is removed to obtain Figure 1b structure shown.
[0057] Next, a floating gate material layer 105 is deposited to cover the oxide layer 102 and the shallow trench oxide 104, to obtain the following Figure 1c structure shown.
[0058] planarizing the floating gate material layer 105 and the shallow trench oxide 104 to a smaller thickness, such as Figure 1d shown.
[0059] Etching back the shallow trench oxide 104 to the oxide layer 102 to form openings in the floating gate material layer...
Embodiment 1
[0064] Step 201 is executed to provide a substrate 201 on which a high voltage oxide layer 203 and a tunnel oxide layer 202 are respectively formed on different regions.
[0065] Specifically, such as Figure 3a As shown, the base 201 includes at least a semiconductor substrate, and the semiconductor substrate can be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), stack-on-insulator Silicon germanium (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.
[0066] Wherein, the tunnel oxide layer 202 and the high voltage oxide layer 203 can be formed by the following method, but the method is only exemplary, and the method includes: first forming the high voltage oxide layer 203 on the substrate , wherein, the high voltage oxide layer 203 can be selected from commonly used materials in the field.
[0067] Next, part of the high voltage oxide layer 203 is removed to expose the ...
Embodiment 2
[0119] The present invention also provides an embedded flash memory, comprising:
[0120] base;
[0121] a high voltage oxide layer and a tunnel oxide layer in different regions of the substrate;
[0122] a shallow trench isolation structure, the bottom of which is embedded in the substrate;
[0123] active regions located in the substrate and isolated from each other by the shallow trench isolation structure;
[0124] T-shaped floating gates are arranged at intervals on the active region, and the horizontal part of the T-shaped floating gate covers part of the top of the shallow trench isolation structure.
[0125] Wherein, the critical dimension at the top of the T-shaped floating gate is 60-130 nm, and the critical dimension at the bottom is 50-75 nm.
[0126] The thickness of the shallow trench isolation structure is 100-1000 angstroms.
[0127] The embedded flash memory further includes:
[0128] an isolation layer located above the T-shaped floating gate;
[0129] ...
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