308results about "DC level change" patented technology

The present invention is a converter stage for converting a differential logic input signal and a corresponding common mode differential logic signal each having a first single-ended logic signal and a complementary second single-ended logic signal into a single-ended logic output signal. The converter stage comprises a first and a second differential stage each having a first and a second MOS transistor and a first and second current source for the differential stages. According to the invention the current sources are controlled by the voltage level which is centered between the mid-potentials of the common mode level differential logic signal and the mid-potential of the differential logic input signal.

A circuit and method are provided for switching in a semiconductor based high power switch. Complementary p-type based transistors are utilized along insertion loss insensitive paths allowing biasing voltages to alternate between supply and ground, allowing for negative voltage supplies and blocking capacitors to be dispensed with, while improving performance.

The invention provides a large-current pulse LD laser driving power supply, comprising a discharging unit; the discharging unit comprises a bias circuit used for calculating the voltage reduction of external loads, and the bias circuit comprises a first MOS tube, a first resister, a second resister, a first variable resister and a first capacitor; the drain of the first MOS tube is connected with the cathode terminal of external load; the source of the first MOS tube is grounded by the first resister; the grid of the first MOS tube is connected with the first variable resister by the second resister so as to obtain a constant voltage value; the grid of the first MOS tube is also grounded by the first capacitor so as to stabilize the voltage. The large-current pulse LD laser driving power supply realizes large-current power supply to the load, realizes the self-adaptability of the external load, realizes the constant current charging to the energy-storage capacitor, is beneficial to improving the charging efficiency and protecting the energy-storage capacitor and realizes the protection of the multi-path protection circuit on the LD load and the power supply.

A supply voltage is divided to provide a divided supply voltage. The divided supply voltage is compared with the reference voltage. The supply voltage is controlled based on the result of comparison so that the supply voltage does not exceed a predetermined breakdown voltage.

Systems and methods for insuring successful initiation of a resonating micro-electro mechanical systems (MEMS). An example system includes a resonating sensor, a drive device, a charge amplifier, and a voltage gain circuit. At start up, the charge amplifier and voltage gain circuit receives signals from the resonating sensor, compensates this signal for DC offsets, and generates a clock signal for the drive, thus placing the resonating sensor in a steady state operating mode. The circuit includes a plurality of gain switches that are toggled to produce a glitch in the signal associated with the received signal. The glitch overcomes the DC offset. A comparator generates the clock signal for the drive device if a signal associated with the received signal exceeds a reference signal.

A system is presented for latching and amplifying a capacitively coupled inter-chip communication signal that operates by receiving an input signal on a capacitive receiver pad and feeding the input signal through an inverter to produce an output signal. The output signal is fed back through a weakened inverter to produce a feedback signal that is fed into an input of the inverter to form a latch for the input signal. The weakened inverter is biased to produce a feedback signal that swings between a high bias voltage, VH, and a low bias voltage, VL. VH is set slightly higher than the switching threshold of the inverter, and VL is set slightly lower than the switching threshold. This feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal.

This invention describes circuits and methods which can allow multiple radar receiver chips to be adjusted to have very low phase offset between them. Multiple receiver chips are used in frequency-modulated carrier-wave (FMCW) radar systems for beamforming to enable angle-of-arrival measurements. FMCW radar systems are widely used in collision-avoidance and adaptive cruise control systems in vehicles, which today are operating in the 76-81 GHz frequency band. In a multi-receiver system, each receive element must have a well-controlled phase response which can be calibrated over process, voltage, and temperature. Without calibration, phase offsets can result in erroneous beamforming receiver measurements. The inventive circuit provides a technique to adjust the phase of multiple receivers across multiple chips using a single local oscillator reference and built-in-test circuitry which consist of phase shifters, a multi-frequency nonlinear phase detection circuit, and power coupling circuits.

A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion of the inverter through a capacitor means. In this manner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided. A level shifter of the CK signal is generated from an output pulse of the shift register, therefore, the low power consumption shift register having the level shifter which flows a shoot-through current for a short period can be provided.

Methods and apparatus are provided for separating DC and AC components of a composite signal Is=Idc+Iac from a current source, e.g., a photodiode current source. Four current mirrors CM-1 . . . CM-4 are used with common branches and overlap. CM-1 through CM-3 mirror Is and CM-4 mirrors Idc where Iac has been removed by a frequency selective branch. Outputs of the Cm-3 and Cm-4 are combined at a node to provide a signal proportional substantially only to Iac. Complementary devices are used where Cm-1 and Cm-4 are of one type and Cm-2 and Cm-3 are of opposite type. The arrangement allows detection of AC signals (e.g., pulses) that are orders of magnitude smaller than the DC background. An I-to-V converter with a large feedback resistance is used at the output to produce a comparatively large voltage output proportional to Iac.

A level-shifter is combined with a bi-directional shift register. The level shifter turns a start signal of the bi-directional shift register to be an enable signal, and (i) activates a level shifting section by supplying a stationary current, during a period in which the enable signal is HIGH, while (ii) deactivates the level shifting section by cutting off the stationary current, during a period in which the enable signal EN is LOW. With this, it is possible to reduce unnecessary current consumption by a level shifter provided for a signal which does not frequently change, such as a shifting direction switching signal for which the bi-directional shift register is provided. At the same time, when such a signal changes, the change is followed with no time lag.

Provided is a differential signal driver capable of operating at a high speed at a low voltage of 1.8V. The differential signal driver includes: a differential-signal driving circuit for switching input differential signals and outputting a common mode voltage through first and second output nodes; and a common-mode feedback circuit for providing a predetermined current to the differential-signal driving circuit or receiving a predetermined current from the differential-signal driving circuit in response to the common mode voltage. The differential-signal driving circuit includes a common-mode voltage output circuit for connecting the first output node to the second output node and generating the common mode voltage of the differential-signal driving circuit. The differential input signals are received through two bipolar transistors.

The intermediate node of the first terminator connected between a pair of signal lines transmitting the first differential signal with one side of the third differential signal as a common voltage and the intermediate node of the second terminator connected between a pair of signal lines transmitting the second differential signal with the other side of the third differential signal as a common voltage are connected by the intermediate connection. Thus, the intermediate node of the first terminator and the intermediate node of the second terminator act as a virtual ground of the third differential signal, enabling the matching of the impedance of the terminators related to the third differential signal and the impedance of the signal lines related to the third differential signal. It is thus able to prevent the reflection of the third differential signal.

A DC offset cancellation circuit that is capable of canceling a DC offset voltage occurring between a pair of differential output signals of a differential amplification circuit, while preventing a signal waveform from being distorted due to accumulation of AC components and a photo-electric pulse conversion circuit that is capable of generating an electrical pulse signal that accurately reproduces a rise timing and a fall timing of an optical pulse signal by canceling the DC offset voltage are provided. A photo-electric pulse conversion circuit is provided with a photodiode, an I-V conversion circuit, a first differential amplification circuit having a DC offset cancellation circuit, a second differential amplification circuit, a reference voltage generation circuit, and a comparison circuit. The DC offset cancellation circuit uses a changeover circuit to change a state of a low-pass filter with a hold function in synchronization with an inversion electrical pulse signal, and performs a negative feedback of a filtered signal which is generated by subjecting third differential signals to low-pass filtration or a hold filtered signal which is a filtered signal held during changeover.

A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion of the inverter through a capacitor means. In this manner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided. A level shifter of the CK signal is generated from an output pulse of the shift register, therefore, the low power consumption shift register having the level shifter which flows a shoot-through current for a short period can be provided