48 results about "Diffusion transistor" patented technology

A method of manufacturing a semiconductor device, such as a double-diffused metal oxide semiconductor (DMOS) transistor, where a first layer may be formed on a semiconductor substrate, with isolation trenches formed in the first layer and semiconductor substrate, and with the trenches being filled with an isolation layer. A second layer may be formed on the first layer and semiconductor substrate, and a plurality of drain trenches may be formed therein. A pair of plug-type drains may be formed in the trenches, to be separated from the isolation layer by a dielectric spacer. Gates and source areas may be formed on a resultant structure containing the plug-type drains. Accordingly, current may be increased with a reduction in drain-source on resistance, and an area of the isolation layer can be reduced, as compared to an existing isolation layer, potentially resulting in a reduction in chip area.

The lateral double-diffused MOS transistor includes a drift region of a first conductive type provided on a semiconductor substrate of a second conductive type, and a body diffusion region of the second conductive type formed on the surface within the drift region. The MOS transistor includes a gate electrode formed in such a position as it covers from part of the body diffusion region to part of the drift region located outside the diffusion region via an insulating film. The MOS transistor further includes a source diffusion region of the first conductive type and a drain diffusion region of the first conductive type formed on top of the body diffusion region and top of the drift region, respectively, both of which correspond to both sides of the gate electrode. The drain diffusion region includes a deep diffusion portion which has a 1 / 1000 or more concentration of a peak concentration of the source diffusion region and which is positioned deeper than the source diffusion region.

Semiconductor integrated circuit that prevents breakdown and degradation of a gate oxide film caused by charge-up in manufacturing steps thereof is provided. The circuit includes a gate 12 provided insulated from a transistor diffusion layer 11, wirings 13 and 14 connected to the gate 12, a wiring 15 parallel to and adjacent to the wiring 13, and a wiring 16 connected to the wiring 15. The gate area of the gate 12 is indicated by G_Area, and the gate capacitance of the gate 12 is indicated by G_Cap. The areas of the wirings 13, 14, 15, and 16 are indicated by MG1_Area, MG2_Area, M1_Area, and M2_Area, respectively, and a parasitic capacitance between the wirings 13 and 15 is indicated by M1_Cap. An antenna ratio R1 calculated from the areas is given by an equation R1={(MG1_Area+MG2_Area)+α(M1_Area+M2_Area)} / G_Area. α is a parameter determined by a function of the G_Cap and the M1_Cap. Layout of the wirings is performed so that a relation R1<L1 (which is a specified value that causes damage to a gate oxide film).

The invention discloses a lateral double-diffused transistor and a manufacturing method thereof. The lateral double-diffused transistor comprises a substrate, a well region and a drift region which are located at the top of the substrate, a source region and a drain region which are located in the well region and the drift region respectively, a first dielectric layer located on a surface of the drift region, a first field plate which is located on a surface of the drift region and covers a part of a surface of the first dielectric layer, a second dielectric layer which partially covers the surface of the first field plate and is stacked on a part of the surface of the first dielectric layer, and a second field plate positioned on a surface of the second dielectric layer, wherein the second field plate comprises at least one contact channel. The lateral double-diffusion transistor is advantaged in that a contact channel is used as the second field plate, so the manufacturing process isreduced, a distance between the second field plate and the silicon substrate is increased, a breakdown voltage of the transistor is increased, and the-powered-on resistance is reduced.

The specification describes an improved mechanical electrode structure for MOS transistor devices with elongated runners. It recognizes that shrinking the geometry increases the likelihood of mechanical failure of comb electrode geometries. The mechanical integrity of a comb electrode is improved by interconnecting the electrode fingers in a cross-connected grid. In one embodiment, the transistor device is interconnected with gate fingers on a lower metaliization level, typically the first level metal, with the drain interconnected at a higher metal level. That allows the drain fingers to be cross-connected with a vertical separation between drain and gate comb electrodes. The cross-connect members may be further stabilized by adding beam extensions to the cross-connect members. The beam extensions may be anchored in an interlevel dielectric layer for additional support.

Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.

The invention discloses a manufacturing method of the drift region of a lateral double-diffused transistor. According to the method, an adhesive layer and a mask layer are designed; with the adhesivelayer coating a final dielectric layer adopted as a barrier, anisotropic etching is performed on a second dielectric layer, or second dielectric layer and a third dielectric layer, so that the middleregion of the drift region is opened, primary drift region injection is performed; with the adhesive layer or the third dielectric layer adopted as a barrier, isotropic etching is performed on the second dielectric layer, the adhesive layer or the adhesive layer and the third dielectric layer is / or removed, secondary drift region injection is performed with the second dielectric layer adopted as abarrier; between the two times of drift region injection, only one-time photoetching is needed, so that a linear gradient drift region can be formed. With the manufacturing method adopted, technological process and manufacturing cost are reduced, and requirements for higher turn-off breakdown voltage and lower conduction impedance can be met.

The invention relates to the technical field of semiconductors, and provides a lateral double-diffused transistor and a manufacturing method thereof. The lateral double-diffused transistor includes a straight part and a curved part, and the straight part includes a straight drain end, a straight drift region, a straight source gate and a substrate. , the straight source gate and the substrate are arranged on both sides of the straight drain end, the straight drift region is arranged between the straight drain end, the straight source gate and the substrate; the curved part includes the curved drain end, the curved source gate and the lining The bottom and the curved drift region located between the curved drain end and the curved source gate and the substrate, and a plurality of curved doping strips, wherein the curved drift region, the curved source gate and the substrate are connected to the curved source gate and the substrate. The concentric semi-circular ring structure of the channel drain end is arranged on the periphery of the curved channel drain end in turn, a plurality of curved doping strips are arranged in the curved drift region at intervals, and the extension direction of the center line of at least one curved doping strip is the same as that of the curved channel. The radii of the semicircular structures of the track parts are coincident. Thereby, charge balance can be achieved to improve the breakdown voltage and effectively reduce the source-drain on-resistance.

The invention discloses a gate-controlled bipolar-field effect compound element semiconductor-based lateral double-diffused metal oxide semiconductor transistor. It is isolated from the source and electrically connected to the gate to meet: when the gate is connected to the voltage, the voltage obtained by the base region makes the parasitic bipolar transistor of the device turn on, replacing the base region and the source region in the traditional elemental semiconductor lateral double-diffusion transistor Short-circuited electrode connection. Compared with the traditional device, the invention greatly increases the on-current of the device and reduces the on-resistance of the device while ensuring the same breakdown voltage of the device.

The invention discloses a wide-bandgap semiconductor lateral double-diffusion transistor with a multi-ring electric field modulation substrate. The substrate under the drift region in this structure is a charge compensation polyring structure. The multi-ring charge compensation of the substrate can expand the vertical space charge region of the lateral double-diffused metal oxide semiconductor field effect transistor. The modulation effect simultaneously modulates the surface transverse electric field and the body longitudinal electric field, so that the surface transverse electric field and the body longitudinal electric field are simultaneously optimized. This structure not only breaks through the breakdown voltage saturation problem of the lateral double-diffused transistor due to the limited vertical withstand voltage, but also achieves the simultaneous optimization of the surface lateral electric field and the internal vertical electric field, which can greatly increase the breakdown voltage of the device.

The present disclosure provides a manufacture method of an LDMOS. The manufacture method includes: forming a drift region in a substrate; forming a gate structure on the substrate, the gate structure defining a source region and a drain region which are separated from each other, and the gate structure including a gate oxide layer and a gate conductor layer which are successively stacked on the substrate; forming a first doped region in the source region, wherein the first doped region is surrounded by the drift region; forming a first barrier layer with a first opening on the source region and in connect with sidewall of the gate structure; forming a first implantation region in the source region through self-aligned implantation on the basis of the first opening of the first barrier layer; and forming a second implantation region and a third implantation region respectively.

The present invention provides a lateral double-diffusion transistor, the main part region of the lateral double-diffusion transistor includes a first transistor, a second transistor and a first ESD device arranged between the first transistor and the second transistor; the first transistor A transistor and a second transistor have a common source terminal, a common drain terminal, a common gate terminal and a common body terminal; the first ESD device includes a cathode connected to the common gate terminal , and two positive poles arranged on the left and right sides of the negative pole, the two positive poles are connected to the common source terminal; the secondary part area includes a second ESD device, and the input of the second ESD device The terminal is connected to the common gate terminal, and the output terminal is grounded. The invention can overcome the damage caused by non-uniform turn-on of the device when ESD surges from the drain end in the prior art, so as to improve the ESD prevention capability of the device.

The invention discloses an elemental semiconductor lateral super-junction double-diffused transistor with a multi-ring electric field modulation substrate. A substrate under a drift region in the structure is of a charge compensation multi-ring structure. The substrate multi-ring charge compensation can help expand the longitudinal space charge region of a lateral double-diffused metal oxide semiconductor field effect transistor. Moreover, the multi-ring structure can introduce a new electric field peak to the distribution of the surface transverse electric field and the inside longitudinal electric field, and can eliminate the substrate assisted depletion problem of super junction. The surface transverse electric field and the inside longitudinal electric field are simultaneously modulated using the electric field modulation effect, so that the surface transverse electric field and the inside longitudinal electric field can be simultaneously optimized. The structure not only breaks through the breakdown voltage saturation problem due to the limited longitudinal withstand voltage of the lateral double-diffused transistor, but also can eliminate the substrate assisted depletion problem of super junction, make the surface transverse electric field and the inside longitudinal electric field simultaneously optimized and greatly improve the breakdown voltage of the device.

A method for forming a transistor device comprising implanting a diffusion-inhibiting species in a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator layer having one or more gate structures formed thereon such that a diffusion inhibiting species is disposed in a portion of the semiconductor-on-insulator layer corresponding to the channel region, and in a portion of the buried insulator layer associated with the source and In the part corresponding to the drain region. Transistor dopant species are introduced in the source and drain regions. The anneal is performed to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.