398 results about "Analogue filter" patented technology

A data-modulated ultra wideband transmitter that modulates the phase, frequency, bandwidth, amplitude and / or attenuation of ultra-wideband (UWB) pulses. The transmitter confines or band-limits UWB signals within spectral limits for use in communication, positioning, and / or radar applications. One embodiment comprises a low-level UWB source (e.g., an impulse generator or time-gated oscillator (fixed or voltage-controlled)), a waveform adapter (e.g., digital or analog filter, pulse shaper, and / or voltage variable attenuator), a power amplifier, and an antenna to radiate a band-limited and / or modulated UWB or wideband signals. In a special case where the oscillator has zero frequency and outputs a DC bias, a low-level impulse generator impulse-excites a bandpass filter to produce an UWB signal having an adjustable center frequency and desired bandwidth based on a characteristic of the filter. In another embodiment, a low-level impulse signal is approximated by a time-gated continuous-wave oscillator to produce an extremely wide bandwidth pulse with deterministic center frequency and bandwidth characteristics. The UWB signal may be modulated to carry multi-megabit per second digital data, or may be used in object detection or for ranging applications. Activation of the power amplifier may be time-gated in cadence with the UWB source thereby to reduce inter-pulse power consumption. The UWB transmitter is capable of extremely high pulse repetition frequencies (PRFs) and data rates in the hundreds of megabits per second or more, frequency agility on a pulse-to-pulse basis allowing frequency hopping if desired, and extensibility from below HF to millimeter wave frequencies.

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit, a digital filter circuit, a data detector circuit, a mimic filter circuit, and a sample clock generation circuit. The analog to digital converter circuit is operable to receive a data input and to provide corresponding digital samples. The digital filter circuit is operable to receive the digital samples and to provide a filtered output. The data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output. The mimic filter circuit is operable to receive the digital samples and to provide a mimicked output. The sample clock generation circuit is operable to provide a sample clock based at least in part on the detected output and the mimicked output.

A system and method for the detection of plasma excursions, such as arcs, micro-arcs, or other plasma instability, during plasma processing by directly monitoring RF current just prior to reaching an RF power electrode of a plasma processing chamber is provided. The monitored RF current may be converted to an RF voltage and then passed through a succession of analog filters and amplifiers to provide a plasma excursion signal. The plasma excursion signal is compared to a preset value, and at points where the plasma excursion signal exceeds the preset value, an alarm signal is generated. The alarm signal is then fed back into a system controller so that an operator can be alerted and / or the processing system can be shut down. In one embodiment, the RF current amplified and converted to a digital signal for digital filtering and processing. In certain embodiments, multiple processing regions can be monitored by a single detection control unit.

A system and a method for channel equalization are provided. A linear equalizer using a continuous-time linear equalization and a decision feedback equalizer using a discrete-time decision feedback equalization are integrated together from a hybrid receiver equalizer. The continuous-time linear equalization scheme and the discrete-time decision feedback equalization scheme are blended using a joint adaptation algorithm to form an equalization scheme for inter-symbol interference cancellation in the hybrid receiver equalizer. The hybrid receiver equalizer controls crosstalk while maintaining signal bandwidth and linearity of a signal by the high-order high frequency roll-off of the linear equalizer used. Using this configuration, the hybrid receiver equalizer eliminates the need for adaptive bandwidth controller used in conventional low-pass receiver equalization schemes. The hybrid receiver equalizer can be used in receivers for dual-speed simultaneous transmission on the same physical link. The hybrid receiver equalizer can also be used in receivers for simultaneous forward and back-channel transmission using differential-signaling in multi-Gbps transceivers.

The invention relates to trimming of analogue filters (201) in integrated circuits by means of an automatic adjusting circuit. A local oscillator (202) in the automatic adjusting circuit provides a periodic reference signal (R) to an adjustable phase shifter (203), which on basis thereof, produces a periodic phase shifted signal (R*). A phase detector (204) receives both the periodic reference signal (R) and the phase shifted period signal (R*) and produces a test signal (T) in response to a phase difference between the periodic reference signal (R) and the periodic phase shifted signal (R8). A lowpass filter (205) receives the test signal (T) and generates a level signal (TDC) relative a reference level, e.g. representing a zero voltage. A digital signal processor (207) produces a primary control signal (CS), having a serial format, on basis of the observation signal (M). A serial-to-parallel converter (208) converts the primary control signal (CS) into a control signal (CP) having a parallel signal format. The control signal (CP) influences a magnitude of at least one component value in the adjustable phase shift between the periodic reference signal (R) and the periodic phase shifted signal (R*) attains a calibrated value being as close as possible to a desired value. A latch (210) forwards at least one signal element of the control signal (CP) for setting of at least one component value in the analogue filter (201) in accordance with a setting of at least one component value in the adjustable phase shifter (203) which produces the calibrated value.

The invention relates to a cascaded scheme in which an RRC filter, a modified RRC filter or other digital filter is implemented at a relatively low data rate, such as twice the symbol or chip rate, or 2×. Interpolation filters are used to increase the data rate to a higher data rate, such as 8×. Decimation filters are used to reduce the data rate from a higher rate, such as 8×, to a lower rate, such as 2×. The coefficients of the digital filter may be adjusted to compensate for characteristics of other components across the entire filter chain. Most of the implementation complexity of the filter chain is consolidated into the relatively low rate (such as 2×) digital filter while interpolation or decimation filters can be implemented at very low cost. The compensation capability provided by the digital filter makes design of simple decimation or interpolation filters much easier. The compensation capability provided by the digital filter, along with the relatively high over-sampling rate for the output of the interpolation filter (or the input of the decimation filter), also makes the design of the preceding (or following) analog filters much easier.

Systems and methods described herein provide for low latency active noise cancellation, which alleviates the problems associated with analog filter circuitry. The present technology utilizes low latency digital signal processing techniques that overcome the high latency conventionally associated with conversion between the analog and digital domains. As a result, low latency active noise cancellation is performed utilizing digital filter circuitry which is not subject to the inaccuracies and drift of analog filter components. In doing so, the present technology provides robust, high quality active noise cancellation.

A filter intended to receive a discrete time signal at a sampling clock frequency, comprising a determined number, greater than 2, of filtering units, each filtering unit comprising head capacitors in a number equal to the determined number, assembled in parallel between an input terminal and the terminal of an integration capacitor; and means for connecting, in successive clock cycles in a number equal to the determined number, successively each head capacitor to the input terminal, and for then simultaneously connecting the head capacitors to the integration capacitor, and in which the successive clock cycles during which the head capacitors of a filtering unit are connected to the input terminal are offset by one clock cycle from one filtering unit to the next one.

The invention relates to a continuous-time delta-sigma analog digital converter (10) for converting an analog input signal (IN) to a digital output signal (OUT), comprising an analog filter (20), which filters the analog input signal, a quantifier (30) cycled by a clock signal (CLK), which quantifier quantifies the filtered analog signal transmitted by the analog filter (20) to generate the digital output signal, and a feedback device (40) with at last one digital analog converter, which transmits at least one analog feedback signal based on the digital output signal (OUT) to the analog filter (20). To simplify the feedback without adversely affecting the converter stability and power consumption, provision is made, according to the invention, for the feedback device (40) for generating a feedback signal corresponding to the differentiated output signal of the quantifier, to comprise two digital analog converters (44-1, 44-2) to which the digital output signal (OUT) of the quantifier (30) is transmitted via a delay stage (42-1, 42-2) with different delays, and hose analog output signals are transmitted to an analog subtractor (24-3).