82 results about "Memory polynomial" patented technology

Non-linear interference cancellation techniques are provided for wireless transceivers. Non-linear reduction of interference of a transmit signal on a received signal in a transceiver device, comprises applying the transmit signal to a first non-linear system; applying the received signal to a second non-linear system; and subtracting an output of the first non-linear system output from an output of second non-linear system output to produce an interference mitigated received signal. The first non-linear system and/or the second non-linear system can be to implemented using one or more of a Volterra series and a Generalized Memory Polynomial Model. System parameters of the first non-linear system and/or the second non-linear system are adapted to reduce a power of the interference mitigated received signal.

A power amplifier system including a composite digital predistorter (DPD) ensuring optimized linearity for the power amplifier is described. In this system, a digital-to-analog converter (DAC), an analog filter, a first mixer, and the power amplifier are serially coupled to the composite DPD. A second mixer, a receive gain block, and an analog-to-digital converter (ADC) are serially coupled to the output of the power amplifier. A DPD training component is coupled between the inputs of the composite DPD and the ADC. The composite DPD includes a memory-based DPD, e.g., a memory polynomial (MP) DPD, a memoryless-linearizing DPD, e.g., a look-up table (LUT) DPD, and two multiplexers.

A system and method for linearizing a power amplifier using digital predistortion technique is provided including processing circuitry, the processing circuitry configured to apply a digital predistortion function based on a weighted static polynomial function, a weighted dynamic polynomial function and a threshold parameter which splits the nonlinear transfer characteristics of the device under test into a region where the static nonlinearity predominates and a region where the dynamic distortions predominate.

An electronic device includes a nonlinear power amplifier, a predistortion coefficient calculator, and a memory polynomial predistortion filter coupled to the nonlinear power amplifier and to the predistortion coefficient calculator. The memory polynomial predistortion filter may include a plurality of finite impulse response (FIR) filter stages, and a summer coupled to the plurality of FIR filter stages. The FIR filter stages may functionally operate in parallel or may include a series of FIR filters coupled in parallel.

The invention provides a mixed double-frequency digital pre-distortion model method based on the DDR. The method includes the following steps that a concurrent double-frequency DPD system based on indirect learning is built; an operation sequence is optimized, a one-dimensional LUT achievement model of the 2D-MP is obtained, a one-dimensional LUT achievement model of 2D-MMP is derived, and then aone-dimensional LUT high-frequency concurrent double-frequency DPD achievement scheme and a model are provided; a dynamic deviation function is substituted into a one-order model of the DDR, and a discrete equivalent baseband expression of the one-order DDR model is obtained and extended to be in a synchronic double-frequency mode; a two-dimensional memory polynomial model same-order envelope cross term is introduced, and a new model and a one-dimensional LUT achievement method of the model in an FPGA are obtained. According to the method, the modeling accuracy and the linearization performance better than a simplified two-dimensional memory polynomial model and a traditional DDR model can be obtained; meanwhile, the advantage that achievement can be conveniently conducted through a one-dimensional lookup table is kept, the new model has a good level in the aspects of performance and complexity, and the method is suitable for practical system applying.

The digital predistortion system and method with extended correction bandwidth includes a predistortion system that uses a two-box architecture based on the cascade of a memory polynomial followed by a memoryless predistortion function. The memoryless predistorter is identified offline and used to perform a coarse linearization which cancels out most of the static nonlinearity of the device under test allowing for a reduced observation bandwidth for the synthesis of the memory polynomial predistortion sub-function.

The invention discloses a pre-distortion method for a power amplifier. The pre-distortion method includes the steps that transmitting signals x(k) are received; the transmitting signals x(k) are substituted into a pre-distortion relational expression which is established according to the characteristics of the power amplifier and is based on a memory polynomial, the transmitting signals x(k) are subjected to pre-distortion in combination with a lookup table, pre-distorted transmitting signals y(k) are obtained, and the pre-distorted transmitting signals y(k) are sent to the power amplifier for power amplification and output. It is thus clear that before the transmitting signals x(k) are sent to the power amplifier, the transmitting signals x(k) are subjected to pre-distortion through the pre-distortion relational expression which is established according to the characteristics of the power amplifier and is based on the memory polynomial, distortion caused by non-linearity of the power amplifier and generated when the pre-distorted transmitting signals y(k) pass through the power amplifier is offset, optimal performance transmission of the transmitting signals x(k) is guaranteed, radio frequency transmitting efficiency is improved, and the application range is wide. The invention further discloses a pre-distortion device for the power amplifier and a radio frequency system.

The memory polynomial based digital predistorter utilizes a cluster-based particle swarm optimization (PSO) technique and has an embedded model-size estimator. The PSO technique and model-size estimator efficiently find the dimensions and accurately estimate the coefficients of the memory polynomial based digital predistorter for improved linearity of a power amplifier.