84results about How to "Suppression of floating body effect" patented technology

In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

A body biasing structure of devices connected in series on an SOI substrate is provided. According to some embodiments, the shallow junction of common source / drain regions enables all devices to bias by only one body contact on an SOI substrate like a conventional bulk MOSFET, and the floating body effect on an SOI substrate can be prevented.

The invention discloses an MOS structure for inhibiting SOI floating-body effect. The MOS structure comprises a substrate, a buried insulating layer positioned above the substrate and an active region positioned above the buried insulating layer, wherein the active region comprises a body region, and a first conduction type source region and a first conduction type drain region which are positioned at the two ends of the body region, and a heavily doped second conduction type region positioned between the first conduction type source region and the buried insulating layer; and a gate region is formed above the body region. When the structure is manufactured, the position of the first conduction type source region is subjected to ion implantation by a mask to make a region positioned on the lower part of the first conduction type source region and above the buried insulating layer form the heavily doped second conduction type region. The MOS structure inhibits the floating-body effect effectively, and has the advantages of no increase of chip area, compatibility of a manufacturing process with the conventional CMOS process and the like.

The invention provides a manufacturing method of a semiconductor structure. The method includes the steps of step 1, providing an SOI substrate and forming a heavy doping buried layer and a surface active layer on the substrate, step 2, forming a grid pile and a side wall on the substrate, step 3, forming an opening in one side of the grid pile, wherein the opening penetrates through the surface active layer and the heavy doping buried layer and stops in a silicon film above an insulation buried layer of the SOI substrate, step4, filling the opening to form a backfill plug, and step 5, forming a source region / drain region, wherein the source region and the heavy doping buried layer are overlapped, and partial drain region is placed in the backfill plug. Correspondingly, the invention further provides the semiconductor structure. According to the semiconductor structure and the manufacturing method thereof, the heavy doping buried layer is beneficial to reducing the width of a source region depletion layer / a drain region depletion layer and restricting the short-channel effect; the heavy doping buried layer and the source region are overlapped to form heavy doping pn junctions, therefore, the floating body effect of SOI MOS devices is effectively restricted, semiconductor device performance is effectively improved, leading out on regions is not needed, and the area and cost of devices are saved.