Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a manufacturing method of a semiconductor structure. The method includes the steps of step 1, providing an SOI substrate and forming a heavy doping buried layer and a surface active layer on the substrate, step 2, forming a grid pile and a side wall on the substrate, step 3, forming an opening in one side of the grid pile, wherein the opening penetrates through the surface active layer and the heavy doping buried layer and stops in a silicon film above an insulation buried layer of the SOI substrate, step4, filling the opening to form a backfill plug, and step 5, forming a source region / drain region, wherein the source region and the heavy doping buried layer are overlapped, and partial drain region is placed in the backfill plug. Correspondingly, the invention further provides the semiconductor structure. According to the semiconductor structure and the manufacturing method thereof, the heavy doping buried layer is beneficial to reducing the width of a source region depletion layer / a drain region depletion layer and restricting the short-channel effect; the heavy doping buried layer and the source region are overlapped to form heavy doping pn junctions, therefore, the floating body effect of SOI MOS devices is effectively restricted, semiconductor device performance is effectively improved, leading out on regions is not needed, and the area and cost of devices are saved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] In order to improve the performance and integration of integrated circuit chips, the feature size of devices has been continuously reduced according to Moore's law, and has now entered the nanometer scale. As the size of devices shrinks, power consumption and leakage current become the most concerned issues. CMOS devices prepared by silicon on insulator SOI (Silicon on Insulator) have many advantages such as high speed, low power consumption, high integration, radiation resistance and no self-locking effect, and have become the preferred structure of deep submicron and nanoscale MOS devices. . SOI MOS devices are divided into two types according to the thickness of the silicon film and the maximum thickness of the surface depletion layer: partially depleted and fully depleted S...

AI Technical Summary

Problems solved by technology

However, as shown in the figure, the source / drain region is in contact with the reverse doped well region, forming a heavily doped pn junction, which has a large junction leakage current, especially at the drain terminal. The large junction leakage current affects the performance of semiconductor devices. performance

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